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US 11,145,758 B2Granted
Fully-depleted CMOS transistors with u-shaped channel
AssigneeInternational Business Machines Corporation
InventorsKangguo Cheng, Robert H. Dennard, Bruce B. Doris, Terence B. Hook
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Abstract
A structure capable of effectively preventing dopant diffusion from source/drain regions into an underlying semiconductor-on-insulator (SOI) layer of fully-depleted SOI transistors with U-shaped channels is provided. By inserting a dopant diffusion barrier layer between an SOI layer of an SOI substrate and a doped extension layer from which source/drain extension regions are derived, the undesired dopant diffusion from the source/drain extension regions into the underlying SOI layer can be prevented.
Claims20
A method of forming a semiconductor structure comprising:
- forming a dopant diffusion barrier layer over a semiconductor-on-insulator (SOI) layer of an SOI substrate;
- forming a doped extension layer over the dopant diffusion barrier layer;
- forming a sacrificial gate structure over a portion of the doped extension layer, the sacrificial gate structure comprising a sacrificial gate stack and a gate spacer present on sidewalls of the sacrificial gate stack, wherein the gate spacer has a surface that is in direct physical contact with a surface of the doped extension layer;
- forming, after forming the sacrificial gate structure, raised source/drain regions over portions of the doped extension layer that are not covered by the sacrificial gate structure wherein the raised source/drain regions have a sidewall edge that is in direct physical contact with a sidewall of the gate spacer;
- forming an interlevel dielectric (ILD) layer on the raised source/drain regions and laterally surrounding the sacrificial gate structure;
- removing the sacrificial gate stack to form a gate cavity, wherein the gate cavity physically exposes a portion of the doped extension layer;
- removing the physically exposed portion of the doped extension layer, a portion of the dopant diffusion barrier layer and a portion of the SOI layer to provide an opening underneath the gate cavity, wherein the opening extends through the doped extension layer and the dopant diffusion barrier layer and partially into the SOI layer to expose a recessed surface of the SOI layer at a bottom of the opening;
- and
- forming a functional gate stack in the gate cavity and the opening.
6 more elements
A method of forming a semiconductor structure comprising:
- forming a dopant diffusion barrier layer over a semiconductor-on-insulator (SOI) layer of an SOI substrate;
- forming a doped extension layer over the dopant diffusion barrier layer;
- forming a sacrificial gate structure over a portion of the doped extension layer, the sacrificial gate structure comprising a sacrificial gate stack and a gate spacer present on sidewalls of the sacrificial gate stack;
- forming raised source/drain regions over portions of the doped extension layer that are not covered by the sacrificial gate structure, wherein the portions of the doped extension layer that are not covered by the sacrificial gate structure are recessed prior to the forming the raised source/drain regions, and wherein the raised source/drain regions contact a recessed surface of the doped extension layer;
- forming an interlevel dielectric (ILD) layer over the raised source/drain regions to laterally surround the sacrificial gate structure;
- removing the sacrificial gate stack to form a gate cavity;
- removing portions of the doped extension layer, the dopant diffusion barrier layer and the SOI layer to provide an opening underneath the gate cavity, wherein the opening extends through the doped extension layer and the dopant diffusion barrier layer and partially into the SOI layer to expose a recessed surface of the SOI layer at a bottom of the opening;
- and
- forming a functional gate stack in the gate cavity and the opening, wherein the raised source/drain regions are composed of a semiconductor material comprising a dopant that has a same conductivity as a dopant present in the doped extension layer, and wherein the semiconductor material that provides the raised source/drain regions is a compositionally same semiconductor material as a semiconductor material that provides the doped extension layer.
6 more elements
A method of forming a semiconductor structure comprising:
- forming a dopant diffusion barrier layer over a semiconductor-on-insulator (SOI) layer of an SOI substrate;
- forming a doped extension layer over the dopant diffusion barrier layer;
- forming a sacrificial gate structure over a portion of the doped extension layer, the sacrificial gate structure comprising a sacrificial gate stack and a gate spacer present on sidewalls of the sacrificial gate stack;
- forming raised source/drain regions over portions of the doped extension layer that are not covered by the sacrificial gate structure, wherein the portions of the doped extension layer that are not covered by the sacrificial gate structure are recessed prior to the forming the raised source/drain regions, and wherein the raised source/drain regions contact a recessed surface of the doped extension layer;
- forming an interlevel dielectric (ILD) layer over the raised source/drain regions to laterally surround the sacrificial gate structure;
- removing the sacrificial gate stack to form a gate cavity;
- removing portions of the doped extension layer, the dopant diffusion barrier layer and the SOI layer to provide an opening underneath the gate cavity, wherein the opening extends through the doped extension layer and the dopant diffusion barrier layer and partially into the SOI layer to expose a recessed surface of the SOI layer at a bottom of the opening;
- and
- forming a functional gate stack in the gate cavity and the opening, wherein the raised source/drain regions are composed of a semiconductor material comprising a dopant that has a same conductivity as a dopant present in the doped extension layer, and wherein the semiconductor material that provides the raised source/drain regions is a compositionally different semiconductor material than a semiconductor material that provides the doped extension layer.
6 more elements
Dependencies are inferred from the claim text.