Semiconductor device with dummy fin and liner and method of forming the same

A method of forming a semiconductor device, comprising:

• forming a semiconductor stack including alternate first semiconductor layers and second semiconductor layers over a substrate, wherein the first semiconductor layers and the second semiconductor layers include different materials and are stacked up along a direction generally perpendicular to a top surface of the substrate;
• conformally depositing a dielectric liner along a sidewall of the semiconductor stack;
• forming a dummy fin structure along a sidewall of the dielectric liner;
• forming a dummy gate structure over the semiconductor stack;
• forming a spacer structure wrapping edge portions of the first semiconductor layers;
• and
• replacing the dummy gate structure with a metal gate structure wrapping middle portions of the first semiconductor layers.

A method of forming a semiconductor device, comprising:

• forming a semiconductor stack including alternate first semiconductor layers and second semiconductor layers over a substrate, wherein the first semiconductor layers and the second semiconductor layers include different materials and are stacked up along a direction generally perpendicular to a top surface of the substrate;
• depositing a third semiconductor layer around the semiconductor stack, wherein the third semiconductor layer includes the same material as the second semiconductor layers;
• conformally depositing a dielectric liner along a sidewall of the third semiconductor layer;
• forming a dummy fin structure along the dielectric liner;
• forming a dummy gate structure over the semiconductor stack;
• forming a gate spacer along a sidewall of the dummy gate structure;
• forming an inner spacer between edge portions of the first semiconductor layers;
• removing the dummy gate structure to form a gate trench;
• selectively removing the second semiconductor layers, the third semiconductor layer, and a portion of the dielectric liner exposed in the gate trench;
• and
• forming a metal gate structure wrapping middle portions of the first semiconductor layers exposed in the gate trench.