Field-effect transistors with dual thickness gate dielectrics

An electronic device, comprising:

• an input/output (I/O) port;
• a receiver circuit, having an input coupled to the I/O port;
• an electrostatic discharge protection (ESD) circuit, coupled to the I/O port and to the input of the receiver circuit;
• and
• a diode,
• wherein:
• the ESD circuit includes a transistor having a source region, a drain region, and a gate stack,
• each of the source region and the gate stack is coupled to a ground potential,
• the ESD circuit is coupled to the I/O port and to the input of the receiver circuit by having the drain region coupled to the I/O port and to the input of the receiver circuit, and
• the diode is coupled between the ground potential and the I/O port.

A method of forming a transistor arrangement, the method comprising:

• providing a source region and a drain region in a semiconductor material;
• and
• providing a gate stack over a portion of the semiconductor material that is between the source region and the drain region, wherein the portion includes a first portion and a second portion, and the gate stack includes:
• one or more gate electrode materials,
• a first gate dielectric between the first portion of the semiconductor material and the one or more gate electrode materials, and
• a second gate dielectric between the second portion of the semiconductor material and the one or more gate electrode materials,
• wherein:
• a thickness of the first gate dielectric is different from a thickness of the second gate dielectric,
• at least a portion of the first portion includes dopants of a first type at a dopant concentration between 1×1016 and 1×1018 dopant atoms per cubic centimeter, and
• at least a portion of the second portion or a portion of the semiconductor material that is between the second portion and the drain region includes dopants of a second type at a dopant concentration between 1×1016 and 1×1018 dopant atoms per cubic centimeter.