Heavily doped buried layer to reduce MOSFET off capacitance
AssigneeAnalog Devices, Inc.
InventorsPengfei Wu, Susan L. Feindt, F. Jacob Steigerwald
Life of this patent
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Abstract
A metal-oxide semiconductor field effect transistor (MOSFET) includes a source region and a drain region of a first conductivity type. The MOSFET additionally include a body region of a second conductivity type, where the body region underlies at least a portion of the source region and the drain region. The MOSFET further includes a buried region of the first conductivity type, where the buried region is disposed between the body region and a substrate, where the buried region is configured to reduce a capacitance between the source region and the drain region in response to an indicated voltage applied between the body region and the buried region.
Claims21
A circuit to operate a metal-oxide semiconductor field effect transistor (MOSFET), the circuit comprising:
- a MOSFET comprising:
- a source region and a drain region of a first conductivity type;
- a body region of a second conductivity type, the body region underlying at least a portion of the source region and the drain region;
- and
- a buried region of the first conductivity type, the buried region disposed between the body region and a substrate, the buried region configured with a dopant concentration or at a distance from the source or drain region to reduce a capacitance between the source region and the drain region by depleting the body region adjacent to the drain region or the source region responsive to a reverse bias voltage applied to the body region;
- and
- a sub-circuit coupled to the body region to selectively apply the reverse bias voltage to the body region when the MOSFET is turned off and selectively remove the reverse bias voltage when the MOSFET is turned on.
A method of operating a circuit comprising a metal-oxide semiconductor field effect transistor (MOSFET) to reduce off capacitance of the MOSFET, the method comprising:
- obtaining a MOSFET comprising:
- a source region and a drain region of a first conductivity type;
- a body region of a second conductivity type, the body region underlying at least a portion of the source region and the drain region;
- and
- a buried region of the first conductivity type, the buried region disposed between the body, region and a substrate, the buried region configured to reduce a capacitance between the source region and the drain region in response to an indicated voltage applied between the body region and the buried region;
- fixedly coupling a first voltage to the buried region;
- reducing the off capacitance of the MOSFET by coupling a second voltage to the body region to reverse bias a junction between the body region and the buried region when the MOSFET is turned off;
- and
- coupling the first voltage or a third voltage to the body region to remove the reverse bias of the junction between the body region and the buried region when the MOSFET is turned on.
A circuit to selectively adjust an off capacitance of a metal-oxide semiconductor field effect transistor (MOSFET), the circuit comprising:
- a MOSFET formed on a substrate, the MOSFET comprising:
- a source region and a drain region of a first conductivity type,
- a body region of a second conductivity type disposed adjacent to the source region and the drain region, and a buried region of the first conductivity type, the buried region underlying at least a part of the body region;
- and
- a sub-circuit configured to:
- provide a reverse biasing voltage between the body region and the buried region when the MOSFET is turned off, and
- provide equal voltages to the body region and the buried region when the MOSFET is turned on.
Dependencies are inferred from the claim text.