MOS-based power semiconductor device having increased current carrying area and method of fabricating same
AssigneePurdue Research Foundation
InventorJames A. Cooper
Life of this patent
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Abstract
A semiconductor device fabrication method includes forming first and second spaced apart base regions and source regions in a substrate with a portion of a drift region therebetween. The method further includes forming at least a first trench extending laterally through the base region, the drift region and the source region, the first trench extending vertically partially through the source region. The method also includes forming a first oxide layer over the trenched upper surface, and forming a polysilicon layer over the first oxide layer. The polysilicon layer is patterned to form the gate conductor, and a drain contact is formed on a bottom surface of the semiconductor substrate.
Claims17
A method of fabricating a semiconductor device, comprising:
- a) providing a semiconductor substrate having a bottom layer having a first dopant type and first dopant concentration, and a top layer having the first dopant type and a second dopant concentration that is less than the first dopant concentration;
- b) forming first and second spaced apart base regions in the top layer with at least a portion of a drift region therebetween;
- c) forming first and second spaced apart source regions such that a portion of each of the first and second base regions is disposed between each corresponding first and second source region and the drift region;
- d) forming at least a first trench extending laterally through the base regions, the drift region and the source regions, the first trench extending vertically partially through the source regions, thereby forming a trenched upper surface exposing portions of the first and second source regions, the drift region, and first and second base regions;
- e) forming a first oxide layer over the trenched upper surface;
- f) forming a polysilicon layer over the first oxide layer;
- g) patterning the polysilicon layer to form a gate conductor, the gate conductor disposed vertically above the drift region, and laterally positioned to overlap in the lateral direction with the first and second source regions;
- h) forming a drain contact on a bottom surface of the bottom layer.
A method of fabricating a semiconductor device, comprising:
- a) providing a semiconductor substrate having a bottom layer having a first dopant type and first dopant concentration, and a top layer having the first dopant type and a second dopant concentration that is less than the first dopant concentration;
- b) forming first and second spaced apart base strips in the top layer with at least a strip of a drift region therebetween, the base strips and strip of the drift region extending lengthwise and in a parallel manner in a first direction;
- c) forming first and second spaced apart source strips extending lengthwise the first direction, and such that a portion of each of the first and second base strips is disposed between each corresponding first and second source strip and the strip of the drift region;
- d) forming at least a first trench extending transverse the first direction through the base strips, the strip of the drift region and the source strips, thereby removing portions of the first and second source strips and portions of the first and second base strips, such that the first trench extends vertically partially through the source strips;
- e) forming a first oxide layer over the trenched upper surface;
- f) forming a polysilicon layer over the first oxide layer;
- g) patterning the polysilicon layer to form a gate conductor, the gate conductor disposed vertically above the drift layer, and laterally positioned to overlap in the lateral direction with the first and second source strips;
- and
- h) forming a drain contact on a bottom surface of the bottom layer.
Dependencies are inferred from the claim text.