Cellular insulated gate power device with edge design to prevent failure near edge

An insulated gate controlled device formed as a die comprising:

• a first semiconductor layer of a first conductivity type;
• a second semiconductor layer of a second conductivity type overlying the first semiconductor layer;
• a third semiconductor layer of the first conductivity type overlying the second semiconductor layer;
• a fourth semiconductor layer of the second conductivity type overlying the third semiconductor layer;
• a matrix of cells comprising inner cells and at least one edge cell, wherein each of the inner cells and the at least one edge cell comprises an associated insulated gate within a trench formed at least within the third semiconductor layer to form vertical field effect devices in the inner cells and the at least one edge cell,
• wherein a vertical structure of npn and pnp transistors is formed, and conduction between the first semiconductor layer and the fourth semiconductor layer is controlled by a voltage applied to the gates;
• and
• wherein the at least one edge cell is formed differently from the inner cells to conduct a current that is lower than a current conducted by an inner cell, when the insulated gate controlled device is in its on state, by implementing one or more of the following:
• providing positive ions in a gate dielectric layer along sidewalls of the trenches for the inner cells to cause the field effect device in the at least one edge cell to have a threshold voltage that is greater than the threshold voltage of the field effect devices in the inner cells, or
• providing negative ions in the gate dielectric layer along sidewalls of the trench for the at least one edge cell to cause the field effect device in the at least one edge cell to have a threshold voltage that is greater than the threshold voltage of the field effect devices in the inner cells.

An insulated gate controlled device formed as a die comprising:

• a first semiconductor layer of a first conductivity type;
• a second semiconductor layer of a second conductivity type overlying the first semiconductor layer;
• a third semiconductor layer of the first conductivity type overlying the second semiconductor layer;
• a fourth semiconductor layer of the second conductivity type overlying the third semiconductor layer;
• a matrix of cells comprising inner cells and at least one edge cell, wherein each of the inner cells and the at least one edge cell comprises an associated insulated gate within a trench formed at least within the third semiconductor layer to form vertical field effect devices in the inner cells and the at least one edge cell,
• wherein a vertical structure of npn and pnp transistors is formed, and conduction between the first semiconductor layer and the fourth semiconductor layer is controlled by a voltage applied to the gates;
• and
• a resistive layer between the edge cell and the first electrode electrically contacting the inner cells and the at least one edge cell, so that the at least one edge cell conducts a current that is lower than a current conducted by an inner cell, when the insulated gate controlled device is in its on state.