US 11,145,713 B2Granted

High voltage metal-oxide-semiconductor (HVMOS) device integrated with a high voltage junction termination (HVJT) device

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsKarthick Murukesan, Wen-Chih Chiang, Chun Lin Tsai, Ker-Hsiao Huo, Kuo-Ming Wu, Po-Chih Chen, Ru-Yi Su, Shiuan-Jeng Lin, Yi-Min Chen, Hung-Chou Lin, Yi-Cheng Chiu

Life of this patent

Estimating the term…

patentgrep

Loading patent…

Abstract

Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well.

Claims20

Dependent claims

An integrated circuit (IC) comprising:

a substrate;
a first switching device well and a termination device well bordering in the substrate and having a first doping type;
a first switching device overlying the first switching device well, wherein the first switching device comprises a body well and a gate electrode, wherein the body well has a second doping type opposite the first doping type and is recessed into a top of the first switching device well, and wherein the body well directly contacts the first switching device well at a PN junction underlying the gate electrode;
a peripheral well in the substrate and having the second doping type, wherein the peripheral well has a first sidewall boundary directly contacting the first switching device well continuously in a first closed path and further has a second sidewall boundary directly contacting the termination device well continuously in a second closed path, and wherein the first sidewall boundary is spaced from the body well;
a dielectric structure sunken into the substrate;
a first field plate overlying the second sidewall boundary and on a first sidewall of the dielectric structure;
a spiral structure overlying the first switching device well and the termination device well on the dielectric structure, wherein the dielectric structure extends directly from the first field plate to the spiral structure;
a high side well overlying the termination device well in the substrate and having the second doping type, wherein the high side well has a first sidewall boundary that directly contacts the termination device well continuously in a third closed path surrounded by the second closed path, but not the first closed path;
a second field plate on a second sidewall of the dielectric structure, wherein the dielectric structure extends continuously and linearly from the second field plate to the spiral structure;
and
a contact region extending laterally and continuously along a boundary of the high side well in a fourth closed path, wherein the contact region is spaced from the high side well and borders the second field plate.

8 more elements

An integrated circuit (IC) comprising:

a substrate;
a termination device well in the substrate and having a first doping type;
a high side well overlying the termination device well in the substrate and having a second doping type opposite the first doping type, wherein the high side well has a sidewall boundary directly contacting the termination device well continuously in a first closed path;
a first switching device and a second switching device in the substrate, respectively at a first lateral recess and a second lateral recess in the high side well;
a peripheral well in the substrate and having the second doping type, wherein the peripheral well separates and individually surrounds the first and second switching devices and the termination device well;
a termination device contact region in the substrate, wherein the termination device contact region is on the termination device well and has the first doping type;
and
a first dielectric structure sunken into the substrate, wherein the first dielectric structure overlies the sidewall boundary, and adjoins the termination device contact region, continuously along an entirety of the first closed path.

5 more elements

An integrated circuit (IC) comprising:

a substrate;
a termination device well in the substrate and having a first doping type;
a first switching device bordering the termination device well in the substrate and comprising a body well, a drift well, and a gate electrode, wherein the drift and body wells are in the substrate and respectively have the first doping type and a second doping type opposite the first doping type, and wherein the drift and body wells directly contact at a PN junction underlying the gate electrode;
a high side well overlying the termination device well in the substrate and having the second doping type;
a termination device contact region in the substrate and on the termination device well, wherein the termination device contact region has the first doping type and extends laterally along a boundary of the high side well in a first closed path;
a peripheral well in the substrate and having the second doping type, wherein the peripheral well has a first sidewall boundary extending around the first switching device in a second closed path and further has a second sidewall boundary directly contacting the termination device well in a third closed path, and wherein the first sidewall boundary directly contacts the drift well and is completely spaced from the body well;
and
a high side contact region overlying the high side well in the substrate and having the second doping type, wherein the high side contact region is ring shaped;
wherein the peripheral well has a protrusion that is buried in the termination device well and protrudes laterally to and terminates at a third sidewall boundary of the peripheral well directly under the termination device contact region;
wherein the protrusion has a first segment and a second segment, wherein the first and second segments are respectively on opposite sides of the high side well and protrude towards each other, wherein the first segment is separated from the high side contact region by a first distance, and wherein the second segment is separated from the high side contact region by a second distance that is the same as the first distance.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/601,998Filed 15 Oct 2019 · continuation
Priority: 28 Sep 2017
Published: US 2020/0044014 A16 Feb 2020
Granted: 12 Oct 2021
Term ends: Not estimatedThe source records don’t support an estimate.

Classification21 codes

H10D 62/109
By having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination…
H03K 19/018507
Using field effect transistors only: interface arrangements
H10D 30/0281
Of double-diffused metal oxide semiconductor [DMOS] FETs: of lateral dmos [ldmos] fets
H10D 30/603
Having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs: having asymmetry in the channel direction, e.g. lateral…

Family

Application62/564,695Us provisional application · filed 28 Sep 2017
Application15/964,636Parent of this continuation · filed 27 Apr 2018
US 2020/0044014 A1Pre-grant publication · published 6 Feb 2020
US 10,535,730 B2Parent of this continuation
US 2019/0096988 A1Published application
US 11,145,713 B2This patent

From the US filing history. Foreign family members aren’t listed.