Method for manufacturing active matrix board

A method for manufacturing an active matrix board including

• a display region including a plurality of pixel regions, a peripheral region located around the display region,
• a substrate, and oxide semiconductor TFTs which are supported with the substrate and each of which is placed in a corresponding one of the pixel regions,
• each of the pixel regions including
• a light-shielding layer which is placed on the substrate and which has conductivity;
• a lower insulating layer covering the light-shielding layer;
• an oxide semiconductor layer which is placed on the lower insulating layer, which includes a channel region overlapping the light-shielding layer when viewed in a substrate surface normal direction, and which also includes a source contact region and drain contact region located on both sides of the oxide semiconductor layer;
• a gate insulating layer placed on the channel region of the oxide semiconductor layer;
• a gate electrode placed on the gate insulating layer;
• an interlayer insulating layer covering the gate electrode and the oxide semiconductor layer;
• a source electrode;
• and a drain electrode, the source electrode and the drain electrode being connected to the source contact region and the drain contact region, respectively, in a source contact hole and drain contact hole, respectively, formed in the interlayer insulating layer,
• the peripheral region including
• a lower conductive layer formed from the same conductive film as the light-shielding layer and
• an upper conductive layer formed from the same conductive film as the source electrode and the drain electrode, the upper conductive layer being connected to the lower conductive layer in a connecting portion contact hole formed in the interlayer insulating layer and the lower insulating layer, the method comprising:
• (A) a step of forming the light-shielding layer and the lower conductive layer on the substrate;
• (B) a step of forming the lower insulating layer such that the lower insulating layer covers the light-shielding layer and the lower conductive layer;
• (C) a step of forming the oxide semiconductor layer, the gate insulating layer, and the gate electrode on the lower insulating layer;
• (D) a step of forming the interlayer insulating layer such that the interlayer insulating layer covers the gate electrode and the oxide semiconductor layer;
• (E) a step of forming the source contact hole and the drain contact hole in the interlayer insulating layer such that a portion of the source contact region of the oxide semiconductor layer and a portion of the drain contact region thereof are exposed and forming the connecting portion contact hole in the interlayer insulating layer and the lower insulating layer such that a portion of the lower conductive layer is exposed;
• and
• (F) a step of forming the source electrode, the drain electrode, and the upper conductive layer on the interlayer insulating layer,
• the step (E) including
• (e-1) a step of forming a photoresist film on the interlayer insulating layer and
• (e-2) a step of forming a photoresist layer in such a manner that the photoresist film is exposed to light using a multi-tone mask and is then developed,
• the photoresist layer including
• a first region having a first thickness,
• a second region which has a second thickness less than the first thickness and which overlaps a portion of the source contact region, a third region which has the second thickness and which overlaps a portion of the drain contact region, and
• a first opening portion overlapping the portion of the lower conductive layer.