Memory device and multi-level memory cell having ferroelectric storage element and magneto-resistive storage element

A multi-level memory cell, comprising:

• a ferroelectric memory element, configured to store a first bit of a multi-bit data;
• a magneto-resistive storage element, configured to store a second bit of the multi-bit data,
• wherein the ferroelectric storage element is cascaded to the magneto-resistive storage element,
• the ferroelectric storage element is formed in a front-end-of-line processing of a semiconductor fabrication, and
• the magneto-resistive storage element is formed in a back-end-of-line processing of the semiconductor fabrication.

A method, adapted to a memory device having a plurality of multi-level memory cells, each of the plurality of multi-level memory cells comprises a ferroelectric storage element and a magneto-resistive storage element, the method comprising:

• storing a first bit of a multi-bit data to the ferroelectric storage element of a multi-level memory cell among the plurality of multi-level memory cells;
• and
• storing second bit of the multi-bit data to the magneto-resistive storage element of the multi-level memory cell among the plurality of multi-level memory cells, wherein the ferroelectric storage element is cascaded to the magneto-resistive storage element,
• wherein the ferroelectric storage element is formed in a front-end-of-line processing of a semiconductor fabrication, the magneto-resistive storage element is formed in a back-end-of-line processing of the semiconductor fabrication.