US 11,145,674 B1Granted

3D memory device and method of manufacturing the same

AssigneeMacronix International Co., Ltd.

InventorsWei-Liang Lin, Wen-Jer Tsai

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Abstract

A 3D memory device includes a substrate, stacked structures formed on the substrate, common source line (CSL) contacts, and NOR flash memories. The substrate has CSLs and memory cell regions alternately arranged along one direction in parallel. The stacked structures are located on the memory cell regions and include a ground select line (GSL) layer and a word line (WL) layer. The CSL contacts are disposed along another direction to connect the CSLs. The NOR flash memories are disposed in the memory cell regions, and each of the NOR flash memories includes at least an epitaxial pillar through the stacked structure, a charge-trapping layer located between the epitaxial pillar and the WL layer, and a high-k layer located between the charge-trapping layer and the WL layer. The epitaxial pillar has a retracted sidewall at a position passing through the GSL layer.

Claims10

Dependent claims

A 3D memory device, comprising:

a substrate having a plurality of common source lines (CSLs) and a plurality of memory cell regions alternately arranged along a first direction in parallel;
a plurality of stacked structures formed on the plurality of memory cell regions of the substrate, and each of the stacked structures comprises a ground select line (GSL) layer electrically isolated from the substrate and a word line (WL) layer electrically isolated from the GSL and formed thereon;
a plurality of CSL contacts formed on the plurality of CSLs of the substrate along a second direction to connect each of the CSLs;
and
a plurality of NOR flash memories passing through the stacked structures and disposed in the plurality of memory cell regions, and each of the NOR flash memories comprises:
an epitaxial pillar formed from the substrate, and the epitaxial pillar has a retracted sidewall at a portion passing through the GSL layer;
a charge-trapping layer located between the epitaxial pillar and the WL layer in the stacked structure;
a high-k layer located between the charge-trapping layer and the WL layer;
and
a first insulating layer located between the retracted sidewall of the epitaxial pillar and the GSL layer.

7 more elements

A method of manufacturing a 3D memory device, comprising:

providing a substrate having a plurality of common source line (CSL) regions and a plurality of memory cell regions alternately arranged along a first direction in parallel;
forming a stacked structure on the substrate, wherein the stacked structure comprises N+1 layers of a first material layer and N layers of a second material layer alternated with each other, and N is an integer greater than 1;
forming a plurality of through holes in the stacked structure on the plurality of memory cell regions until the substrate is exposed;
growing a plurality of epitaxial pillars from the substrate through the plurality of through holes;
forming a plurality of first slits in the stacked structure on the plurality of CSL regions and exposing a topmost second material layer, wherein each of the first slits is aligned with each of the CSL regions;
completely removing the topmost second material layer to form a first space exposing a portion of each of the epitaxial pillars;
depositing a charge-trapping layer conformally on a surface of the plurality of first slits and a surface of each of the epitaxial pillars exposed;
forming a plurality of second slits exposing the plurality of CSL regions under the plurality of first slits and exposing a bottommost second material layer;
completely removing the bottommost second material layer to form a second space exposing another portion of each of the epitaxial pillars;
performing a thermal oxidation method to form a thermal oxidation layer on the surface of each of the epitaxial pillars exposed and a surface of the plurality of CSL regions;
depositing a high-k layer on a surface of the thermal oxidation layer and a surface of the charge-trapping layer exposed in the first space and the second space;
depositing a metal material in the first space and the second space;
forming a plurality of third slits cutting off the metal material at positions of the original first slits and second slits and exposing the substrate, wherein the metal material located in the first space is used as a word line (WL) and the metal material located in the second space is used as a ground select line (GSL);
performing an ion implantation process to form a plurality of CSLs in the exposed substrate;
depositing an insulating layer in the plurality of third slits;
and
forming a plurality of CSL contacts in the insulating layer, and the plurality of CSL contacts are respectively connected along a second direction.

14 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/841,700Filed 7 Apr 2020
Published: US 2021/0313342 A17 Oct 2021
Granted: 12 Oct 2021
Term ends: Not estimatedThe source records don’t support an estimate.

Classification14 codes

H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/30
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the memory core region
H10B 43/30
EEPROM devices comprising charge-trapping gate insulators: characterised by the memory core region