Semiconductor apparatus with multiple tiers, and methods
AssigneeMicron Technology, Inc.
InventorToru Tanzawa
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Abstract
Apparatus and methods are disclosed, including an apparatus that includes a number of tiers of a first semiconductor material, each tier including at least one access line of at least one memory cell and at least one source, channel and/or drain of at least one peripheral transistor, such as one used in an access line decoder circuit or a data line multiplexing circuit. The apparatus can also include a number of pillars of a second semiconductor material extending through the tiers of the first semiconductor material, each pillar including either a source, channel and/or drain of at least one of the memory cells, or a gate of at least one of the peripheral transistors. Methods of forming such apparatus are also described, along with other embodiments.
Claims21
A memory structure, comprising:
- multiple vertically arranged tiers comprising a first semiconductor material, and comprising an access line of a respective group of memory cells, each of such tiers also including at least one of a source, a channel, and a drain of a respective peripheral transistor;
- and
- multiple pillars of a second semiconductor material extending through the tiers comprising the first semiconductor material, a first pillar of the multiple pillars comprising at least one of a source, a channel, and a drain of each of multiple memory cells, and a second pillar of the multiple pillars formed of a third semiconductor material and comprising a gate of at least one peripheral transistor.
A memory structure, comprising:
- multiple vertically disposed tiers, comprising,
- in a first region, the tiers formed of a first semiconductor material, each tier of the first semiconductor material comprising at least one of a source, a channel, and a drain of a respective peripheral transistor;
- and
- in a second region, the tiers formed of metal, each tier of metal comprising an access line of respective memory cells within an array of memory cells, each portion of a tier formed of metal coupled to a respective portion of the tier formed of semiconductor material.
Dependencies are inferred from the claim text.