Semiconductor device including stack structures having gate pads with different thicknesses

A method of manufacturing a semiconductor device comprising:

• forming a structure having insulating layers and sacrificial layers alternately repeatedly stacked on a substrate and having a step-shaped structure at one side;
• forming additional sacrificial layer patterns disposed on the one side of the structure;
• forming a lower interlayer insulating layer and an upper interlayer insulating layer on the additional sacrificial layer patterns;
• removing some of the additional sacrificial layer patterns;
• forming a channel structure passing through the structure;
• removing the sacrificial layers and the additional sacrificial layer patterns to form an open area;
• forming gate electrodes and gate pads filling the open area;
• and
• forming a contact passing through at least one of the lower interlayer insulating layer and the upper interlayer insulating layer and connected to the gate pads,
• wherein the gate pads extend from one end of the gate electrodes, and comprise a thick pad having a thickness thicker than that of the gate electrodes and a thin pad having the same thickness as that of the gate electrodes, and
• wherein the thin pad comprises:
• a lowermost pad connected to a lowermost gate electrode of the gate electrodes;
• and
• an uppermost pad connected to an uppermost gate electrode of the gate electrodes.

A method of manufacturing a semiconductor device comprising:

• forming a structure having insulating layers and sacrificial layers alternately repeatedly stacked on a substrate and having a step-shaped structure at one side;
• forming additional sacrificial layer patterns disposed on the one side of the structure;
• forming a lower interlayer insulating layer and an upper interlayer insulating layer on the additional sacrificial layer patterns;
• removing some of the additional sacrificial layer patterns;
• forming a channel structure passing through the structure;
• removing the sacrificial layers and the additional sacrificial layer patterns to form an open area;
• forming gate electrodes and gate pads filling the open area;
• and
• forming a contact passing through at least one of the lower interlayer insulating layer and the upper interlayer insulating layer and connected to the gate pads,
• wherein the gate pads extend from one end of the gate electrodes, and comprise a thick pad having a thickness thicker than that of the gate electrodes and a thin pad having the same thickness as that of the gate electrodes,
• wherein the forming of the structure comprises:
• forming a lower structure comprising a stepwise portion;
• and
• forming an upper structure comprising a stepwise portion on the lower structure,
• wherein the forming of the additional sacrificial layer patterns comprises:
• forming additional lower sacrificial layer patterns covering an upper surface and the stepwise portion of the lower structure;
• and
• forming additional upper sacrificial layer patterns covering an upper surface and the stepwise portion of the upper structure, and
• wherein the removing of the some of the additional sacrificial layer patterns comprises:
• removing the additional lower sacrificial layer pattern covering the upper surface of the lower structure among the additional lower sacrificial layer patterns to expose an upper surface of an uppermost lower sacrificial layer of the lower structure.