3D NAND memory device and method of forming the same

A method for manufacturing a three-dimensional memory device, comprising:

• forming a lower memory cell string over a substrate, the lower memory cell string including a plurality of first word lines sequentially stacked over the substrate, a plurality of first insulating layers and a first channel structure, the plurality of first word lines being spaced apart from each other by the plurality of first insulating layers, and the first channel structure passing through the plurality of first word lines and the plurality of first insulating layers, the first channel structure being formed along a direction perpendicular to the substrate, and coupled with the substrate via a bottom channel contact;
• forming an interconnect structure over the lower memory cell string, the interconnect structure being connected with the first channel structure;
• and
• forming an upper memory cell string over the interconnect structure, the upper memory cell string including a plurality of second word lines sequentially stacked over the interconnect structure, a plurality of second insulating layers and a second channel structure, the plurality of second word lines being spaced apart from each other by the plurality of second insulating layers, and the second channel structure passing through the plurality of second word lines and the plurality of second insulating layers, the second channel structure being formed along a direction perpendicular to the substrate, the second channel structure having sidewalls and a bottom portion, the second channel structure extending into the interconnect structure vertically and extending into a lowermost second insulating layer of the plurality of second insulating layers at an interface of the interconnect structure, the second channel structure and the lowermost second insulating layer, a channel dielectric region of the second channel structure being formed above a top surface of the interconnect structure, wherein:
• the second channel structure includes a second channel layer that extends through the plurality of second word lines and extends into the interconnect structure,
• the second channel layer includes (i) a bottom portion that extends into the interconnect structure, (ii) a top portion that has a tapered structure, and (iii) a middle portion that is positioned between the bottom portion and the top portion and adjacent to the interface, the middle portion having a rounded projection that extends away from the top surface of the interconnect structure, and extends outwards into the lowermost second insulating layer, wherein a top of the rounded projection in the middle portion is positioned above a bottom of the tapered structure in the top portion.

A memory cell string, comprising:

• a lower memory cell string formed over a substrate, the lower memory cell string including a plurality of first word lines sequentially stacked over the substrate, a plurality of first insulating layers and a first channel structure, the plurality of first word lines being spaced apart from each other by the plurality of first insulating layers, and the first channel structure passing through the plurality of first word lines and the plurality of first insulating layers, the first channel structure being formed along a direction perpendicular to the substrate, and coupled with the substrate via a bottom channel contact;
• an interconnect structure formed over the lower memory cell string, the interconnect structure being connected with the first channel structure;
• and
• an upper memory cell string formed over the interconnect structure, the upper memory cell string including a plurality of second word lines sequentially stacked over the interconnect structure, a plurality of second insulating layers and a second channel structure, the plurality of second word lines being spaced apart from each other by the plurality of second insulating layers, and the second channel structure passing through the plurality of second word lines and the plurality of second insulating layers, the second channel structure being formed along a direction perpendicular to the substrate, the second channel structure having sidewalls and a bottom portion, the second channel structure extending into the interconnect structure vertically and extending into a lowermost second insulating layer of the plurality of the second insulating layers at an interface of the interconnect structure, the second channel structure and the lowermost second insulating layer, a channel dielectric region of the second channel structure being above a top surface of the interconnect structure,
• wherein:
• the second channel structure includes a second channel layer that extends through the plurality of second word lines and extends into the interconnect structure,
• the second channel layer includes (i) a bottom portion that extends into the interconnect structure, (ii) a top portion that has a tapered structure, and (iii) a middle portion that is positioned between the bottom portion and the top portion and adjacent to the interface, the middle portion having a rounded projection that extends away from the top surface of the interconnect structure, and extends outwards into the lowermost second insulating layer, and
• a top of the rounded projection in the middle portion is positioned above a bottom of the tapered structure in the top portion.