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US 11,145,655 B2Granted
Memory device with reduced-resistance interconnect
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsSahil Preet Singh, Yen-Huei Chen
Life of this patent
Estimating the term…
Abstract
Some embodiments relate to a memory device including first and second conductive lines extending generally in parallel with one another within over a row of memory cells. A centerline extends generally in parallel with the first and second conductive lines and is spaced between the first and second conductive lines. A first plurality of conductive line segments is over the first conductive line. Conductive line segments of the first plurality of conductive line segments are coupled to different locations on the first conductive line. A second plurality of conductive line segments are disposed over the second conductive line, and are coupled to different locations on the second conductive line.
Claims20
A memory device, comprising:
- a first conductive line and a second conductive line extending generally in parallel with one another within a first interconnect layer over a row of memory cells, the first and second conductive lines being coupled to memory cells of the row, wherein a virtual plane may be inserted in parallel with and between the first and second conductive lines in a direction perpendicular to a substrate on which the first and second conductive lines are disposed, the virtual plane being spaced at a first distance from an inner edge of the first conductive line and being spaced at a second distance from an inner edge of the second conductive line, the first and second distances being equal;
- a first plurality of conductive line segments disposed within a second interconnect layer over the first interconnect layer, wherein conductive line segments of the first plurality of conductive line segments are coupled to different locations on the first conductive line and are electrically coupled in parallel with corresponding portions of the first conductive line;
- a second plurality of conductive line segments disposed in the second interconnect layer, wherein conductive line segments of the second plurality of conductive line segments are coupled to different locations on the second conductive line and are electrically coupled in parallel with corresponding portions of the second conductive line, the second plurality of conductive line segments being geometrically parallel to the first plurality of conductive line segments;
- and
- wherein the first conductive line and the second conductive line each extend along a continuous distance over the row of memory cells, and
- wherein individual conductive line segments of the first plurality of conductive line segments alternate with individual conductive line segments of the second plurality of conductive line segments along the virtual plane over the continuous distance.
3 more elements
A memory device, comprising:
- a memory cell array including a plurality of memory cells arranged in rows and columns, each memory cell including at least one access transistor;
- a first conductive line disposed at a first height over a semiconductor substrate and having a continuous length over a row of memory cells, the first conductive line being coupled to a first group of access transistors for the row of memory cells;
- a first plurality of conductive line segments each disposed at a second height greater than the first height over the semiconductor substrate, wherein conductive line segments of the first plurality of conductive line segments are coupled to different locations on the first conductive line and are electrically coupled in parallel with corresponding portions of the first conductive line;
- and
- a second plurality of conductive line segments each disposed at a third height greater than the second height over the semiconductor substrate, wherein conductive line segments of the second plurality of conductive line segments are coupled to different locations on the first conductive line and are electrically coupled in parallel with corresponding portions of the first conductive line;
- wherein individual conductive line segments of the first plurality of conductive line segments alternate with individual conductive line segments of the second plurality of conductive line segments along the continuous length of the first conductive line, such that each individual conductive line segment of the first plurality of conductive line segments is laterally separated from each individual conductive line segment of the second plurality of conductive line segments.
3 more elements
A memory device, comprising:
- a first conductive line and a second conductive line extending generally in parallel with one another within a lower interconnect layer over a row of memory cells, the first conductive line and the second conductive line being coupled to memory cells of the row of memory cells;
- a first plurality of conductive line segments disposed within an intermediate interconnect layer over the lower interconnect layer, wherein conductive line segments of the first plurality of conductive line segments are coupled to different locations on the first conductive line and are electrically coupled in parallel with corresponding parts of the first conductive line;
- and
- a second plurality of conductive line segments being disposed in an upper interconnect layer over the intermediate interconnect layer, wherein conductive line segments of the second plurality of conductive line segments are coupled to different locations on the second conductive line and are electrically coupled in parallel with corresponding portions of the second conductive line,
- wherein each conductive line segment of the second plurality of conductive line segments comprises a lower surface continuously extending laterally from over a first outer sidewall of a corresponding conductive line segment of the first plurality of conductive line segments to over an opposing second outer sidewall of the corresponding conductive line segment of the first plurality of conductive line segments.
2 more elements
Dependencies are inferred from the claim text.