US 11,145,654 B2 · Field effect transistor (FET) comprising channels with silicon germanium (SiGe)

Abstract

A device comprising a substrate and a first transistor formed over the substrate. The first transistor includes a first source disposed over the substrate, a first drain disposed over the substrate, a first plurality of channels coupled to the first source and the first drain, and a first gate surrounding the first plurality of channels. The first plurality of channels is located between the first source and the first drain. At least one channel includes silicon germanium (SiGe). The transistor is a field effect transistor (FET). The transistor is a gate all around (GAA) FET. The transistor may be configured to operate as a negative channel metal oxide semiconductor (NMOS) transistor. The transistor may be configured to operate as a positive channel metal oxide semiconductor (PMOS) transistor.

Claims34

Dependent claims

A device comprising:

a substrate;
and
a first transistor formed over the substrate, the first transistor comprising:
a first source disposed over the substrate;
a first drain disposed over the substrate;
a first plurality of channels coupled to the first source and the first drain,
wherein the first plurality of channels is located between the first source and the first drain, and
wherein at least one channel from the first plurality of channels comprises silicon germanium (SiGe);
a plurality of inner spacers located between the first source and the first drain;
a first gate surrounding the first plurality of channels;
and
a bottom silicon germanium (SiGe) layer located in the substrate.

9 more elements

An integrated device comprising:

a substrate;
a first transistor formed over the substrate, the first transistor comprising:
a first source disposed over the substrate;
a first drain disposed over the substrate;
a first plurality of channels coupled to the first source and the first drain,
wherein the first plurality of channels is located between the first source and the first drain, and
wherein at least one channel from the first plurality of channels comprises silicon germanium (SiGe),
a first plurality of inner spacers located between the first source and the first drain;
a first gate surrounding the first plurality of channels;
and
a first bottom silicon germanium (SiGe) layer located in the substrate, wherein the first bottom silicon germanium (SiGe) layer is located under a channel from the first plurality of channels;
and
a second transistor formed over the substrate, the second transistor comprising:
a second source disposed over the substrate;
a second drain disposed over the substrate;
a second plurality of channels coupled to the second source and the second drain,
wherein the second plurality of channels is located between the second source and the second drain, and
wherein at least one channel from the second plurality of channels comprises silicon germanium (SiGe);
a second plurality of inner spacers located between the second source and the second drain;
a second gate surrounding the second plurality of channels;
and
a second bottom silicon germanium (SiGe) layer located in the substrate, wherein the second bottom silicon germanium (SiGe) layer is located under a channel from the second plurality of channels.

19 more elements

An apparatus comprising:

a substrate;
a first transistor means formed over the substrate, the first transistor means comprising:
a first source disposed over the substrate;
a first drain disposed over the substrate;
a first plurality of channels coupled to the first source and the first drain,
wherein the first plurality of channels is located between the first source and the first drain, and
wherein at least one channel from the first plurality of channels comprises silicon germanium (SiGe);
a first plurality of inner spacers located between the first source and the first drain;
and
a first gate surrounding the first plurality of channels;
and
a first bottom silicon germanium (SiGe) layer located in the substrate, wherein the first bottom silicon germanium (SiGe) layer is located under a channel from the first plurality of channels;
and
a second transistor means formed over the substrate, the second transistor means comprising:
a second source disposed over the substrate;
a second drain disposed over the substrate;
a second plurality of channels coupled to the second source and the second drain,
wherein the second plurality of channels is located between the second source and the second drain, and
wherein at least one channel from the second plurality of channels comprises silicon germanium (SiGe);
a second plurality of inner spacers located between the second source and the second drain;
and
a second gate surrounding the second plurality of channels;
and
a second bottom silicon germanium (SiGe) layer located in the substrate, wherein the second bottom silicon germanium (SiGe) layer is located under a channel from the second plurality of channels.

21 more elements

Dependencies are inferred from the claim text.

Field effect transistor (FET) comprising channels with silicon germanium (SiGe)

Life of this patent

Field effect transistor (FET) comprising channels with silicon germanium (SiGe)

Life of this patent

Abstract

Claims34