Multi-threshold gate structure with doped gate dielectric layer

A method, comprising:

• depositing a gate dielectric layer on first and second pluralities of semiconductor layers;
• depositing a first dopant layer around each semiconductor layer of the first and second pluralities of semiconductor layers;
• removing portions of the first dopant layer deposited around the second plurality of semiconductor layers;
• depositing a second dopant layer on remaining portions of the first dopant layer and around each semiconductor layer of the second plurality of semiconductor layers;
• and
• performing an anneal process on the gate dielectric layer, the remaining portions of the first dopant layer, and the second dopant layer.

A method, comprising:

• forming a first gate dielectric layer with a first atomic dopant ratio, comprising:
• depositing an intrinsic gate dielectric material;
• depositing first and second dopant layers on a first portion of the intrinsic gate dielectric material;
• and
• performing an anneal process on the first portion of the intrinsic gate dielectric material and the first and second dopant layers;
• and
• forming a second gate dielectric layer having a second atomic dopant ratio lower than the first atomic dopant ratio, comprising:
• depositing the second dopant layer on a second portion of the intrinsic gate dielectric material;
• and
• performing the anneal process on the second portion of the intrinsic gate dielectric material and the second dopant layer.