Tipless transistors, short-tip transistors, and methods and circuits therefor

An integrated circuit, comprising:

• a plurality of first deeply depleted channel (DDC) transistors formed in a substrate and having controllable source-drain current paths coupled between a first and second node, the first DDC transistors having a first source and a first drain, the first DDC transistors having first extension regions that extend in a lateral direction on an inner side of the first source and the first drain, and under a gate electrode of the first DDC transistors, the first DDC transistors being configured to selectively couple a first output node to the first or second node in response to one or more input signals, the first DDC transistors having drawn gate lengths of less than one micron;
• a plurality of second deeply depleted channel (DDC) transistors formed in the substrate and having controllable source-drain current paths coupled between the first node and the second node, the second DDC transistors having a second source and a second drain, the second DDC transistors having second extension regions that extend in a lateral direction on an inner side of the second source and the second drain, and under a gate electrode of the second DDC transistors, the second extension regions extend to a lesser extent in a lateral direction than the first extension regions, the second DDC transistors being configured to selectively couple a second output node to the first or second node in response to the one or more input signals, the second DDC transistors having drawn gate lengths of less than one micron.