Semiconductor package including a substrate having two silicon layers formed on each other
AssigneeSamsung Electronics Co., Ltd.
InventorsYanggyoo Jung, Chulwoo Kim, Hyo-Chang Ryu, Yun Seok Choi
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Abstract
A semiconductor package may include a package substrate, a first interposer substrate mounted on the package substrate, and a first semiconductor chip disposed on the first interposer substrate. The first interposer substrate may include a first base layer, a second base layer disposed on the first base layer, circuit patterns provided in each of the first base layer and the second base layer, and an integrated device embedded in the first base layer and connected to at least one of the circuit patterns. A top surface of the first base layer may contact a bottom surface of the second base layer.
Claims19
A semiconductor package, comprising:
- a package substrate;
- a first interposer substrate mounted on the package substrate;
- and
- a first semiconductor chip disposed on the first interposer substrate,
- wherein the first interposer substrate comprises:
- a first base layer;
- a second base layer disposed on the first base layer;
- circuit patterns provided in each of the first base layer and the second base layer and including horizontally-extending interconnection lines at least in the first base layer;
- and
- an integrated circuit device embedded in the first base layer and connected to at least one of the circuit patterns,
- wherein a top surface of the first base layer contacts a bottom surface of the second base layer,
- wherein the first base layer and the second base layer are each formed of silicon (Si), and
- wherein the integrated circuit device is a capacitor or an active device that comprises a first conductive layer extending horizontally and at the same vertical level within the first base layer as at least one of the horizontally-extending interconnection lines.
A semiconductor package, comprising:
- a package substrate;
- a first silicon interposer disposed on the package substrate, the first silicon interposer including an interconnection pattern that includes a horizontally-extending interconnection line directly connected to a vertically-extending through electrode;
- a second silicon interposer disposed on the first silicon interposer, the second silicon interposer including a through electrode;
- and
- at least one semiconductor chip mounted on the second silicon interposer,
- wherein surfaces of the first silicon interposer and the second silicon interposer connect to each other at a boundary interface, such that the interconnection pattern and the through electrode are directly connected to each other,
- wherein the first silicon interposer further comprises an integrated circuit device provided therein, and
- wherein the integrated circuit device is a capacitor or an active device that comprises a first conductive layer extending horizontally and at the same vertical level within the first silicon interposer as the horizontally-extending interconnection line.
Dependencies are inferred from the claim text.