US 11,145,633 B2 · Semiconductor package and manufacturing method thereof

Abstract

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a semiconductor die an insulating encapsulation laterally covering the semiconductor die. The semiconductor die includes a semiconductor substrate, a plurality of conductive pads distributed over the semiconductor substrate, a plurality of conductive vias disposed on and electrically connected to the conductive pads, and a dielectric layer disposed over the semiconductor substrate and spaced the conductive vias apart from one another. A sidewall of the dielectric layer extends along sidewalls of the conductive vias, the conductive vias are recessed from a top surface of the dielectric layer, and a sloped surface of the dielectric layer is connected to the top surface of the dielectric layer and the sidewall of the dielectric layer.

Claims20

Dependent claims

A semiconductor package, comprising:

a semiconductor die comprising:
a semiconductor substrate;
a plurality of conductive pads distributed over the semiconductor substrate;
a plurality of conductive vias disposed on and electrically connected to the conductive pads;
and
a dielectric layer disposed over the semiconductor substrate and spacing the conductive vias apart from one another, a sidewall of the dielectric layer extending along sidewalls of the conductive vias, the conductive vias being recessed from a top surface of the dielectric layer, and a sloped surface of the dielectric layer connected to the top surface of the dielectric layer and the sidewall of the dielectric layer;
and
an insulating encapsulation laterally covering the semiconductor die.

5 more elements

Dependencies are inferred from the claim text.

Semiconductor package and manufacturing method thereof

Life of this patent

Semiconductor package and manufacturing method thereof

Life of this patent

Abstract

Claims20