Semiconductor package and manufacturing method thereof

A semiconductor package manufacturing method, comprising:

• providing a first semiconductor die, wherein the first semiconductor die comprises an active surface and a back surface that are opposite to each other;
• forming a first redistribution layer on the active surface of the first semiconductor die, wherein the first redistribution layer is electrically connected to the first semiconductor die;
• stacking a second semiconductor die on the first redistribution layer, wherein the second semiconductor die comprises an active surface and a back surface that are opposite to each other, the active surface of the second semiconductor die is oriented toward the first redistribution layer, a plurality of first through-silicon vias are formed in the second semiconductor die, and the second semiconductor die is electrically connected to the first redistribution layer through the plurality of first through-silicon vias;
• forming a plurality of conductive vias on the first redistribution layer, wherein the plurality of conductive vias are located around the second semiconductor die and electrically connected to the first redistribution layer;
• forming an encapsulant on the first redistribution layer, wherein the encapsulant encapsulates the second semiconductor die and the plurality of conductive vias;
• forming a second redistribution layer on the encapsulant, wherein the second redistribution layer is electrically connected to the plurality of conductive vias and the plurality of first through-silicon vias in the second semiconductor die;
• stacking a third semiconductor die on the second redistribution layer, wherein the third semiconductor die comprises an active surface and a back surface that are opposite to each other, the active surface of the third semiconductor die is oriented toward the second redistribution layer, a plurality of second through-silicon vias are formed in the third semiconductor die, and the third semiconductor die is electrically connected to the second redistribution layer through the plurality of second through-silicon vias;
• and
• forming a third redistribution layer on the third semiconductor die, wherein the third redistribution layer is electrically connected to the plurality of second through-silicon vias in the third semiconductor die;
• wherein
• at an overlooking angle from the third semiconductor die to the first semiconductor die, an area of the second semiconductor die is smaller than that of the first semiconductor die, and an area of the third semiconductor die is larger than that of the second semiconductor die.