Back to results
US 11,145,612 B2Granted
Methods for bump planarity control
AssigneeTexas Instruments Incorporated
InventorRafael Jose Lizares Guevara, III
Life of this patent
Estimating the term…
Abstract
A method for manufacturing an integrated circuit package includes depositing a first layer of metal at a location of a first metal post that is for connecting an IC die to an external circuit. The method also includes depositing a second layer of metal at the location of the first metal post, and a first layer of metal at a location of a second metal post that is for connecting the IC die to an external circuit.
Claims17
A method for manufacturing an integrated circuit (IC) package, comprising:
- depositing a first layer of metal at a first location on a redistribution layer of an IC die;
- and
- depositing a second layer of metal at the first location on the first layer of metal, and at a second location on the redistribution layer of the IC die, the second location of the redistribution layer not including the first layer of metal, wherein a cross sectional area of the second layer of metal on the first layer of metal is different than the cross sectional area of the second layer of metal at the second location on the second redistribution layer.
A method for manufacturing an integrated circuit (IC) package, comprising:
- depositing, in a first step, a first layer of a metal on a first metal post of an IC die;
- and
- depositing, in a second step, a second layer of the metal on the first layer of the metal of the first metal post, and a third layer of the metal on a second metal post of the IC die, the second metal post not including the first layer of the metal;
- wherein the first metal post has a round shape and the second metal post has an oval shape, from a top view of the IC package.
1 more element
Dependencies are inferred from the claim text.