Semiconductor package and method of manufacturing the same

A semiconductor package comprising:

• a redistribution insulating layer comprising a first surface and a second surface opposite to each other;
• a first conductive line pattern in the redistribution insulating layer;
• a second conductive line pattern on the first surface of the redistribution insulating layer;
• a lower electrode pad comprising a first portion embedded in the redistribution insulating layer and a second portion protruding from the second surface of the redistribution insulating layer;
• a first conductive via pattern extending between the first conductive line pattern and the lower electrode pad and in contact with the lower electrode pad;
• a second conductive via pattern extending between the second conductive line pattern and the first conductive line pattern;
• and
• a semiconductor chip disposed on the redistribution insulating layer and electrically connected to the second conductive line pattern,
• wherein widths of the first conductive via pattern and the second conductive via pattern are each gradually narrower in a first direction, wherein the first direction is from the first surface of the redistribution insulating layer toward the second surface of the redistribution insulating layer.

A semiconductor package comprising:

• a redistribution structure comprising a plurality of insulating layers, a plurality of conductive line patterns disposed on an upper surface of each of the plurality of insulating layers, and a plurality of conductive via patterns penetrating at least one of the plurality of insulating layers and connected to at least one of the plurality of conductive line patterns;
• a semiconductor chip on an upper surface of the redistribution structure;
• a chip connection terminal interposed between the semiconductor chip and a conductive line pattern of an uppermost layer of the plurality of conductive line patterns;
• an underfill material layer surrounding the chip connection terminal between the semiconductor chip and the redistribution structure;
• a molding layer covering at least a portion of the semiconductor chip;
• a lower electrode pad on a bottom surface of the redistribution structure;
• and
• an external connection terminal on the lower electrode pad,
• wherein the lower electrode pad comprises a first portion embedded in a lowermost insulating layer of the plurality of insulating layers and a second portion protruding from the lowermost insulating layer, and a thickness of the second portion of the lower electrode pad is less than a thickness of the first portion of the lower electrode pad, and
• wherein the lower electrode pad has a rectangular cross-sectional view.