Semiconductor chip including alignment pattern
AssigneeSamsung Electronics Co., Ltd.
InventorsYoon Sung Kim, Yun Hee Kim, Byung Moon Bae, Hyun Su Sim, Jun Ho Yoon, Jung Ho Choi
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Abstract
A semiconductor chip including an alignment pattern is provided. The semiconductor chip includes a substrate associated with a main chip region of a semiconductor wafer and including a scribe lane. A lower interlayer insulating layer is disposed on the substrate, a low-K layer including dummy metal patterns is disposed on the lower interlayer insulating layer, an alignment pattern is disposed on the low-K layer, and a passivation layer covers the alignment pattern.
Claims20
A semiconductor chip comprising:
- a substrate associated with a main chip region of a semiconductor wafer and including a scribe lane;
- a lower interlayer insulating layer disposed on the substrate;
- a low-K layer including dummy metal patterns disposed on the lower interlayer insulating layer;
- an alignment pattern disposed on the low-K layer;
- and
- a passivation layer at least partially covering the alignment pattern.
A semiconductor chip comprising:
- a substrate associated with a main chip region of a semiconductor wafer and including a scribe lane surrounding the main chip region;
- a lower interlayer insulating layer disposed on the substrate;
- an alignment key structure including a low-K layer disposed on the lower interlayer insulating layer in the scribe lane, an upper alignment pattern disposed on the low-K layer, and a passivation layer disposed on the upper alignment pattern;
- and
- dummy pattern structures including a low-K pattern disposed on the lower interlayer insulating layer and a lower dummy pattern disposed in the low-K pattern and disposed on at least one side surface of the alignment key structure.
A semiconductor chip comprising:
- a substrate associated with a main chip region of a semiconductor wafer and including a scribe lane;
- a low-K layer configured to extend on the substrate along the scribe lane;
- a lower dummy pattern disposed in the low-K layer;
- a passivation layer disposed on the low-K layer;
- an alignment pattern disposed in the passivation layer;
- and
- an open region in which the low-K layer and the passivation layer are partially removed,
- wherein the lower dummy pattern and the alignment pattern are spaced apart from one another in a lengthwise direction of the scribe lane.
Dependencies are inferred from the claim text.