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US 11,145,599 B2Granted
Method of fabricating a memory device having multiple metal interconnect lines
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorJhon Jhy Liaw
Life of this patent
Estimating the term…
Abstract
Provided is a memory device including an array of memory cells. A first bit-line coupled to memory cells of a first column of the array of memory cells. The first bit-line is disposed on a first metal layer. A second bit-line is coupled to the first bit-line. The second bit-line is disposed on a second metal layer and coupled to the first bit-line by at least one via. A word line is coupled to a row of the array of memory cells.
Claims18
A method of forming a memory device comprising:
- providing a substrate having a pass-gate transistor in a first region and control circuitry in a peripheral region;
- forming a first conductive via extending from a drain region of the transistor;
- depositing a first metal line above the transistor, wherein the first metal line is operable to carry a first bit-line signal to the drain region via the first conductive via;
- forming a second conductive via extending above and connected to the first metal line;
- after depositing the first metal line, depositing a second metal line connected to the first metal line through the second conductive via;
- and
- wherein at least one of the first and second metal lines extends to the control circuitry for the memory device;
- depositing a third metal line;
- forming a third conductive via to a gate of the transistor, wherein the third conductive via is electrically connected to the third metal line;
- and
- depositing a fourth metal line, wherein the fourth metal line is connected to the third metal line by a fourth conductive via, wherein one of the third or fourth metal lines extends to the control circuitry for the memory device.
8 more elements
A method of providing a memory device comprising:
- forming a transistor having a gate structure interposing a drain region and a source region, wherein the gate structure on a semiconductor substrate;
- depositing a first metal line of a first metal layer of a multi-layer interconnect (MLI) structure, wherein the first metal line extends horizontally on the first metal layer and is connected to the drain region;
- forming a first conductive via connected to and extending above the first metal line;
- depositing a landing pad above the first conductive via, wherein the landing pad is disposed on a second metal layer of the MLI structure;
- forming a second conductive via connected to and extending above the landing pad;
- depositing a second metal line above and connected to the second conductive via, the second metal line extending horizontally on a third metal layer of the MLI structure;
- and
- providing a signal to/from the drain region on each of the first metal line and the second metal line to control circuitry.
5 more elements
A method of forming a memory device comprising:
- providing a substrate having a transistor in a first region and control circuitry in a peripheral region;
- forming a first via extending from a drain region of the transistor;
- depositing a first metal line above the first via, wherein the first metal line is operable to carry a first bit-line signal to the drain region via the first via;
- forming a second via extending above and connected to the first metal line;
- after depositing the first metal line, depositing a second metal line connected to the second conductive via, wherein at least one of the first metal line or the second metal line extends to the control circuitry for the memory device;
- forming a third metal line electrically connected to a gate of the transistor;
- and
- forming a fourth metal line, wherein the fourth metal line is connected to the third metal line by a third via, wherein one of the third or fourth metal lines extends to the control circuitry for the memory device.
5 more elements
Dependencies are inferred from the claim text.