Semiconductor package including a pad pattern

A semiconductor package, comprising:

• a first semiconductor chip, the first semiconductor chip comprising:
• a first semiconductor substrate including a first surface and a second surface opposite to the first surface, and the second surface including a first semiconductor substrate recess;
• a first bump pattern on the first surface of the first semiconductor substrate;
• a first through via structure through the first semiconductor substrate from the first surface to a bottom of the recess of the second surface, and an upper surface of the first through via structure protruding from the bottom of the first semiconductor substrate recess;
• a first insulation liner pattern on the second surface of the first semiconductor substrate, an inner surface of the first semiconductor substrate recess and an upper sidewall of the first through via structure;
• and
• a first pad pattern on a surface of the first insulation liner pattern in the first semiconductor substrate recess, the upper surface of the first through via structure, and a portion of the first insulation liner pattern on the second surface of the first semiconductor substrate, wherein the first pad pattern includes a first pad pattern recess having a concave shape;
• a second semiconductor chip, the second semiconductor chip comprising:
• a second semiconductor substrate including a first surface and a second surface opposite to the first surface, and the second surface including a second semiconductor substrate recess;
• a second bump pattern on the first surface of the second semiconductor substrate;
• a second through via structure through the second semiconductor substrate from the first surface to a bottom of the second semiconductor substrate recess of the second surface, and an upper surface of the second through via structure protruding from the bottom of the second semiconductor substrate recess;
• a second insulation liner pattern on the second surface of the second semiconductor substrate, an inner surface of the second semiconductor substrate recess and an upper sidewall of the second through via structure;
• and
• a second pad pattern on a surface of the second insulation liner pattern in the second semiconductor substrate recess, the upper surface of the second through via structure, and a portion of the second insulation liner pattern on the second surface of the second semiconductor substrate, wherein the second pad pattern includes a second pad pattern recess having a concave shape;
• and
• a third semiconductor chip including a third bump pattern on a first surface of a third semiconductor substrate,
• wherein the first semiconductor chip, the second semiconductor chip and the third semiconductor chip are sequentially stacked,
• the second bump pattern of the second semiconductor chip is bonded on the first pad pattern to fill the first pad pattern recess of the first semiconductor chip, and
• the third bump pattern of the third semiconductor chip is bonded on the second pad pattern to fill the second pad pattern recess of the second semiconductor chip.

A semiconductor package, comprising:

• a first semiconductor chip, the first semiconductor chip comprising:
• a first semiconductor substrate including a first surface and a second surface opposite to the first surface, and the second surface including a first semiconductor substrate recess;
• a through via structure through the first semiconductor substrate from the first surface to a bottom of the first semiconductor substrate recess of the second surface, and an upper surface of the through via structure protruding from the bottom of the first semiconductor substrate recess;
• and
• a pad pattern electrically connected to the upper surface of the through via structure, the pad pattern including a first pad pattern recess having a concave shape;
• and
• a second semiconductor chip including a bump pattern bonded on an inside of the first pad pattern recess.