Gate-last process for vertical transport field-effect transistor

An integrated circuit comprising:

• one or more vertical transport field-effect transistors comprising:
• a substrate;
• a plurality of fins disposed over a top surface of the substrate, the plurality of fins comprising channels for the one or more vertical transport field-effect transistors;
• and
• a gate stack surrounding at least a portion of the plurality of fins, the gate stack comprising a gate dielectric layer, a work function metal layer, and a gate conductor layer;
• wherein the gate stack comprises a box profile in an area between at least two adjacent ones of the plurality of fins;
• wherein the box profile in the area between the at least two adjacent fins comprises:
• the gate dielectric layer disposed on (i) sidewalls of the two adjacent fins, (ii) portions of a top surface of a bottom spacer extending between the at least two adjacent fins, and (iii) portions of a bottom surface of a top spacer extending between the at least two adjacent fins;
• the work function metal layer disposed on interior surfaces of the gate dielectric layer;
• and
• the gate conductor layer filling a cavity defined by interior surfaces of the work function metal layer.