Nonplanar device and strain-generating channel dielectric

A transistor comprising:

• a fin structure that includes a first portion defined between second portions, wherein the first portion and the second portions of the fin structure each include a first semiconductor layer that includes silicon disposed over a second semiconductor layer that includes silicon and germanium, and further wherein the second portions of the fin structure each further include a third semiconductor layer that includes silicon disposed over the first semiconductor layer;
• a high-k metal gate disposed over and wrapping an upper portion of the first semiconductor layer of the first portion of the fin structure, such that the high-k metal gate is disposed on sidewalls of the upper portion of the first semiconductor layer;
• a dielectric isolation feature disposed over sidewalls of a lower portion of the first semiconductor layer of the first portion of the fin structure, sidewalls of a lower portion of the first semiconductor layer of the second portions of the fin structure, sidewalls of the second semiconductor layer of the first portion of the fin structure, and sidewalls of the second semiconductor layer of the second portions of the fin structure;
• and
• a semiconductor oxide layer disposed between the dielectric isolation feature and the sidewalls of the second semiconductor layer of the first portion of the fin structure, wherein the semiconductor oxide layer includes silicon and germanium.

A device comprising:

• a first transistor that includes:
• a first fin structure that includes a first portion defined between second portions, wherein the first portion and the second portions of the first fin structure each include a first semiconductor layer disposed over a second semiconductor layer, and further wherein the second portions of the first fin structure each further include a third semiconductor layer disposed over the first semiconductor layer,
• a first high-k metal gate disposed over and wrapping an upper portion of the first semiconductor layer of the first portion of the first fin structure, such that the first high-k metal gate is disposed on sidewalls of the upper portion of the first semiconductor layer, and
• a semiconductor oxide layer disposed over sidewalls of the second semiconductor layer of the first portion of the first fin structure;
• a second transistor that includes:
• a second fin structure that includes a third portion defined between fourth portions, wherein the third portion and the fourth portions of the second fin structure each include a fourth semiconductor layer disposed over a fifth semiconductor layer and a sixth semiconductor layer disposed over the fifth semiconductor layer, and further wherein the fourth portions of the second fin structure each further include a seventh semiconductor layer disposed over the sixth semiconductor layer, and
• a second high-k metal gate disposed over and wrapping an upper portion of the sixth semiconductor layer of the third portion of the second fin structure, such that the second high-k metal gate is disposed on sidewalls of the upper portion of the sixth semiconductor layer;
• and
• a dielectric isolation feature disposed over:
• sidewalls of a lower portion of the first semiconductor layer of the first portion of the first fin structure, sidewalls of a lower portion of the first semiconductor layer of the second portions of the first fin structure, sidewalls of the second semiconductor layer of the first portion of the first fin structure, and sidewalls of the second semiconductor layer of the second portions of the first fin structure, and
• sidewalls of a lower portion of the sixth semiconductor layer of the third portion of the second fin structure, sidewalls of a lower portion of the sixth semiconductor layer of the fourth portions of the second fin structure, sidewalls of a lower portion of the fourth semiconductor layer of the third portion of the second fin structure, sidewalls of a lower portion of the fourth semiconductor layer of the fourth portions of the second fin structure, sidewalls of the fifth semiconductor layer of the third portion of the second fin structure, and sidewalls of the fifth semiconductor layer of the fourth portions of the second fin structure.