US 11,145,552 B2Granted

Method of manufacturing semiconductor integrated circuit

AssigneeFuji Electric Co., Ltd.

InventorYoshiaki Toyoda

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Abstract

A semiconductor integrated circuit includes: implanting impurity ions of a p-type at different implantation positions by multiple implantation in a part of an upper portion of a semiconductor layer of an n−-type to form first ion implantation regions; implanting the impurity ions of the p-type at different implantation positions by multiple implantation in another part of the upper portion of the semiconductor layer to form second ion implantation regions; activating the impurity ions in the first ion implantation regions to form a well region, and activating the impurity ions in the second ion implantation regions to form a body region; forming a control element including first and second terminal regions of the n+-type in an upper portion of the well region; and forming an output-stage element including an output terminal region of the n+-type in an upper portion of the body region to be controlled by the control element.

Claims19

Dependent claims

A method of manufacturing a semiconductor integrated circuit, comprising:

implanting impurity ions of a second conductivity-type at different implantation positions by multiple implantation in a part of an upper portion of a semiconductor layer of a first conductivity-type so as to selectively form first ion implantation regions;
implanting the impurity ions of the second conductivity-type at different implantation positions by multiple implantation in another part of the upper portion of the semiconductor layer so as to selectively form second ion implantation regions;
activating the impurity ions in the first ion implantation regions to form a well region of the second conductivity-type, and activating the impurity ions in the second ion implantation regions to form a body region of the second conductivity-type;
forming a control element including first and second terminal regions of the first conductivity-type opposed to each other in an upper portion of the well region;
and
forming an output-stage element including an output terminal region of the first conductivity-type in an upper portion of the body region so as to be controlled by the control element.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/726,287Filed 24 Dec 2019
Priority: JP JP2019-2586315 Feb 2019
Published: US 2020/0266109 A120 Aug 2020
Granted: 12 Oct 2021
Term ends: Not estimatedThe source records don’t support an estimate.

Classification17 codes

H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10D 30/0223
Of FETs having insulated gates [IGFET]: having source and drain regions or source and drain extensions self-aligned to sides of the gate
H10D 30/0297
Of vertical dmos [vdmos] fets: using recessing of the gate electrodes, e.g. to form trench gate electrodes
H10D 30/668
Vertical dmos [vdmos] fets: having trench gate electrodes, e.g. UMOS transistors