Power semiconductor device and method of fabricating the same

A method of fabricating a power semiconductor device, comprising the steps of:

• S1) forming a trench in a semiconductor substrate;
• S2) sequentially forming a first oxide layer and a source polysilicon layer over a surface of the semiconductor substrate, with the first oxide layer covering an inner surface of the trench and the source polysilicon layer filling the trench;
• S3) sequentially etching a portion of the source polysilicon layer and a portion of the first oxide layer to expose the surface of the semiconductor substrate, with a remaining portion of the source polysilicon layer in the trench protruding beyond the surface of the semiconductor substrate and a remaining portion of the first oxide layer in the trench being recessed beneath the surface of the semiconductor substrate, such that a groove is formed at a top of the trench, the groove exposing sidewalls of a top end of the remaining portion of the source polysilicon layer and exposing a portion of the inner surface of the trench proximate the surface of the semiconductor substrate;
• S4) forming a second oxide layer and a gate polysilicon layer, the second oxide layer covering both the exposed portion of the source polysilicon layer and the exposed portion of the inner surface of the trench, the gate polysilicon layer filling the groove and situated over the remaining portion of the first oxide layer, wherein the gate polysilicon layer is recessed beneath the surface of the semiconductor substrate and the gate polysilicon layer has a top surface lower than a top surface of the remaining portion of the source polysilicon layer;
• S5) forming spacers over the sidewalls of the top end of the remaining portion of the source polysilicon layer, the spacers situated over the trench;
• and S6) performing, with the spacers serving as a mask, an implantation process to form a source electrode in the semiconductor substrate adjacent to the trench.