Apparatuses and methods for soft post-package repair
AssigneeMicron Technology, Inc.
InventorAlan J. Wilson
Life of this patent
Estimating the term…
Abstract
Embodiments of the disclosure are drawn to apparatuses and methods for soft post-package repair (SPPR). After packaging, it may be necessary to perform post-package repair operations on rows of the memory. During a scan mode of an SPPR operation, addresses provided by a fuse bank may be examined to determine if they are open addresses or if the bad row of memory is a redundant row of memory. The open addresses and the bad redundant addresses may be stored in volatile storage elements, such as in latch circuits. During a soft send mode of a SPPR operation, the address previously associated with the bad row of memory may be associated with the open address instead, and the address of the bad redundant row may be disabled.
Claims21
An apparatus comprising:
- a row latch associated with a redundant word line of a memory array;
- a fuse array configured to store a first address;
- a fuse logic circuit comprising volatile memory elements configured to store a second address, the fuse logic circuit configured to
- determine if the first address is associated with the row latch,
- determine if the first address is associated with a bad redundant row,
- provide the first address to the row latch if the first address is associated with the row latch and the first address is not associated with the bad redundant row, and
- provide the second address to the row latch if the first address is not associated with the row latch.
An apparatus comprising:
- a memory bank comprising a plurality of wordlines;
- a plurality of row latches, each of the row latches associated with one of the wordlines;
- a fuse array configured to store a plurality of addresses and provide the plurality of addresses along a fuse bus;
- and
- a fuse logic circuit configured to receive the plurality of addresses along the fuse bus from the fuse array and provide the plurality of addresses to the row latches, wherein the fuse logic circuit is configured to
- determine if an address of the plurality of addresses is an open fuse bank address and store the open fuse bank address in a first latch bank,
- determine if an address of the plurality of addresses is a bad redundant address and store the bad redundant address in a second latch bank,
- repair a bad row address by providing the bad row address on the fuse bus instead of the open fuse bank address in the plurality of addresses provided to the row latches, and
- disable the bad redundant address and provide the disabled bad redundant address instead of the bad redundant address in the plurality of addresses provided to the row latches.
A method comprising:
- performing a scan mode operation comprising:
- determining if a fuse bank is an open fuse bank and storing an address of the open fuse bank in a first latch bank;
- and
- determining if a row is a bad redundant row and storing an address of the bad redundant row in a second latch bank;
- and
- performing a soft send mode operation comprising:
- repairing a faulty address by associating the faulty address with a row latch associated with the address of the open fuse bank;
- disabling the address of the bad redundant row.
Dependencies are inferred from the claim text.