Chip testing method, device, electronic apparatus and computer readable medium

A chip testing device, comprising:

• a parameter reading interface, configured to determine a language rule of a chip to be tested, and to determine product and timing specifications of the chip to be tested;
• a test pattern library module, configured to generate, based on a plurality of test patterns, a test pattern library, wherein the plurality of test patterns comprises:
• a fast read operation test pattern, a fast write operation test pattern, a fast read/write operation test pattern, a self-refreshing test pattern, a refreshing test pattern, a ZQ calibration test pattern, a mode register setting test pattern, and pre-charge power-down test pattern;
• a code generating module, configured to select, according to the language rule and the product and timing specifications, a test pattern from the test pattern library, and to generate, according to the product and timing specifications and the selected test pattern, a test code;
• and
• a high-speed test machine, configured to automatically test, using the test code, the chip to be tested.

A chip testing device, comprising:

• an information module, configured to acquire related information of a chip to be tested;
• a pattern library, configured to store a plurality of test patterns, wherein the plurality of test patterns comprises:
• a fast read operation test pattern, a fast write operation test pattern, a fast read/write operation test pattern, a self-refreshing test pattern, a refreshing test pattern, a ZQ calibration test pattern, a mode register setting test pattern, and a pre-charge power-down test pattern;
• a native random pattern creator configured to generate a target test pattern for testing the chip to be tested according to information in the information module and content of a database, wherein the target test pattern is one of the plurality of test patterns;
• a format conversion module, configured to insert, according to product and timing specifications, a timing sequence into the target test pattern, wherein the target test pattern with the timing sequence is converted, by a high-speed test machine, to generate a test code, wherein the test code is configured to automatically test the chip to be tested using the target test pattern with the timing sequence.

An electronic apparatus, comprising:

• one or more processors;
• and
• a memory device, configured to store one or more programs;
• wherein, upon being executed by the one or more processors, the one or more programs cause the one or more processors to perform operations, comprising:
• determining a language rule of a chip to be tested;
• determining product and timing specifications of the chip to be tested;
• generating, based on a plurality of test patterns, a test pattern library, wherein the plurality of test patterns comprises:
• a fast read operation test pattern, a fast write operation test pattern, a fast read/write operation test pattern, a self-refreshing test pattern, a refreshing test pattern, a ZQ calibration test pattern, a mode register setting test pattern, and a pre-charge power-down test pattern;
• selecting, according to the language rule and the product and timing specifications, a test pattern from the test pattern library;
• generating, according to the product and timing specifications and the selected test pattern, a test code;
• and
• automatically testing, using the test code, the chip to be tested.

A non-transitory computer readable medium, storing a computer program executable by a processor,

• wherein, upon being executed by the processor, the computer program causes the processor to perform operations, comprising:
• determining a language rule of a chip to be tested;
• determining product and timing specifications of the chip to be tested;
• generating, based on a plurality of test patterns, a test pattern library, wherein the plurality of test patterns comprises:
• a fast read operation test pattern, a fast write operation test pattern, a fast read/write operation test pattern, a self-refreshing test pattern, a refreshing test pattern, a ZQ calibration test pattern, a mode register setting test pattern, and a pre-charge power-down test pattern;
• selecting, according to the language rule and the product and timing specifications, a test pattern from the test pattern library;
• generating, according to the product and timing specifications and the selected test pattern, a test code;
• and
• automatically testing, using the test code, the chip to be tested.