Non-volatile memory with a well bias generation circuit

A method comprising:

• biasing a node of a first circuit at a reference voltage with a control circuit, the control circuit including a first input to receive a signal indicative of a voltage of the node and a second input to receive a second signal indicative of the reference voltage;
• providing a signal indicative of a leakage current through the node;
• controlling a well bias voltage based on a relationship between the signal indicative of the leakage current and a signal indicative of a reference leakage current;
• biasing a well of the first circuit with the well bias voltage.

A circuit comprising:

• a leakage current measuring circuit including:
• a first circuit including bias input node and a well bias node;
• a bias input node control circuit, the bias input node control circuit including a first input to receive an indication of a reference voltage, a second input to receive an indication of a voltage of the bias input node, and an output to bias the bias input node at the reference voltage based on a relationship between the first input and the second input;
• and
• an output to provide a signal indicative of a leakage current of the first circuit through the bias input node;
• a well voltage bias circuit including:
• an output bias node for providing a well bias voltage;
• and
• a well bias control circuit including a first input to receive the signal indicative of the leakage current, a second input to receive a signal indicative of a reference leakage current value, and an output for controlling the well bias voltage at the output bias node based on a relationship between the first input of the well bias control circuit and the second input of the well bias control circuit;
• and
• a memory array circuit including a plurality of memory cells, a plurality of transistors, and an array well bias input coupled to the output bias node to receive the well bias voltage to bias a well of the memory array, wherein the first circuit is a reference circuit configured to emulate a leakage current of the memory array.