Memory with test function and test method thereof
AssigneePowerchip Semiconductor Manufacturing Corporation
InventorYasuhiro Konishi
Life of this patent
Estimating the term…
Abstract
A memory with a test function and a method thereof. The memory includes a memory array having cells, input buffers divided into even- and odd-numbered groups and output buffers divided into even- and odd-numbered groups; at least two data input pads, respectively providing test data to the cells through the even-numbered and the odd-numbered input buffers; a first and a second logic gates, respectively performing a first logic operation on outputs of the even-numbered and odd-numbered output buffers; a third logic gate, performing a second logic operation on outputs of the first and the second logic gates; and at least one data output pad, coupled to an output of the third logic gate for providing a test result of the cells.
Claims17
A memory with a test function, comprising:
- a memory array having cells and a plurality of input buffers and a plurality of output buffers, wherein the plurality of input buffers is divided into even-numbered input buffers and odd-numbered input buffers, and the plurality of output buffers is divided into even-numbered output buffers and odd-numbered output buffers;
- at least two data input pads, respectively providing test data to the cells through the even-numbered input buffers and the odd-numbered input buffers in a test write mode;
- a first logic gate, performing a first logic operation on all outputs of the even-numbered output buffers in a test read mode;
- a second logic gate, performing the first logic operation on all outputs of the odd-numbered output buffers in the test read mode;
- and
- a third logic gate, performing a second logic operation on outputs of the first and the second logic gates;
- and
- at least one data output pad, coupled to an output of the third logic gate for providing a test result of the cells.
A method for testing a memory, the memory having a memory array with a plurality of even-numbered and odd-numbered input buffers and a plurality of even-numbered and odd-numbered output buffers, the method comprising:
- writing test data into cells of the memory under test through the plurality of even-numbered and odd-numbered input buffers through at least two data input pads,
- reading the test data from the cells through the plurality of even-numbered and odd-numbered output buffers;
- performing a first logic operation on all outputs of the plurality of even-numbered output buffers to obtain a first logic value and on all outputs of the plurality of odd-numbered output buffers to obtain a second logic value;
- performing a second logic operation on the first and the second logic values to output a third logic value on at least one data output pad;
- and
- determines whether the cells are defective or not based on the third logic value.
Dependencies are inferred from the claim text.