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US 11,145,379 B2Granted
Electronic fuse cell array structure
AssigneeKey Foundry Co., Ltd.
InventorsJong Min Cho, Sung Bum Park, Kee Sik Ahn, Seong Jun Park
Life of this patent
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Abstract
An eFuse cell array includes a first unit cell and a second unit cell, each including a PN diode, a cell read transistor, and a fuse element. A first placement order of the PN diode, the cell read transistor, and the fuse element in the first unit cell is reversed with respect to a second placement order of the PN diode, the cell read transistor, and the fuse element in the second unit cell.
Claims30
An eFuse cell array comprising:
- a first unit cell and a second unit cell, each comprising:
- a PN diode;
- a cell read transistor;
- and
- a fuse element,
- wherein a position of the PN diode in the first unit cell is diametrically opposed to a position of the PN diode in the second unit cell, and
- wherein a first placement order of the PN diode, the cell read transistor, and the fuse element in the first unit cell is reversed with respect to a second placement order of the PN diode, the cell read transistor, and the fuse element in the second unit cell.
4 more elements
An eFuse cell array comprising:
- a write wordline configured for a write operation;
- a read wordline configured for a read operation;
- a bitline disposed orthogonally to the write wordline and the read wordline;
- a PN diode coupled to the write wordline;
- a cell read transistor coupled to the read wordline;
- and
- a fuse element coupled to the bitline.
4 more elements
An eFuse cell array comprising:
- a memory element coupled to a bitline;
- a PN diode configured to couple the memory element to a write wordline;
- a cell read transistor coupled to the memory element and a gate of the cell read transistor coupled to a read wordline;
- a shared read transistor configured to couple the memory element through the bitline to a ground;
- and
- a shared program transistor coupled to the memory element through the bitline.
3 more elements
An eFuse cell array comprising:
- a plurality of unit cells each comprising a memory element coupled to a bitline, a diode configured to couple the memory element to a write wordline, and a cell read transistor coupled to the memory element and a read wordline;
- a shared read transistor configured to couple the memory element through the bitline to a ground;
- and
- a shared program transistor coupled to the memory element through the bitline,
- wherein a first placement order of the memory element, the cell read transistor, and the diode in odd ones of the plurality of unit cells is reversed with respect to a second placement order of the memory element, the cell read transistor, and the diode in even ones of the plurality of unit cells.
2 more elements
Dependencies are inferred from the claim text.