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US 11,145,377 B2Granted
Memory arrangement and method for operating or testing a memory arrangement
AssigneeAms AG
InventorsGregor Schatzberger, Friedrich Peter Leisenberger, Peter Sarson
Life of this patent
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Abstract
A memory arrangement comprises a non-volatile memory plane (2), a replacement plane (3), an address select block (302), and a counter arrangement (300) having at least one counter (310 to 312). The at least one counter (310 to 312) is configured to be incremented at a write cycle of the memory arrangement (1). The address select block (302) is configured to switch from the non-volatile memory plane (2) to the replacement plane (3), if a counter value of the at least one counter (310 to 312) is higher than a predetermined limit.
Claims7
A memory arrangement, comprising
- a non-volatile memory plane,
- a replacement plane,
- an address select block, and
- a counter arrangement comprising a first number N of counters,
- wherein the non-volatile memory plane comprises a second number M of preselected bit cells with the second number M equal or smaller than the first number N,
- wherein one of the first number N of counters is incremented at a write cycle of a corresponding preselected bit cell of the second number M of preselected bit cells and the address select block switches from the preselected bit cell to a corresponding replacement bit cell of the replacement plane, if the counter value of said counter is higher than a predetermined limit corresponding to said preselected bit cell,
- wherein the memory arrangement comprises an address replacement plane for storing the addresses of the second number M of preselected bit cells,
- wherein the addresses of the second number M of preselected bit cells are determined in a test phase, the test phase is before an operation phase and the preselected bit cells are not changed in the operation phase,
- wherein an erase test is performed in the test phase,
- wherein the erase test of a bit cell (20) is performed by
- programming the bit cell (20),
- determining a first value (Icell1) of a bit cell current (ICELL) flowing through the bit cell (20),
- providing an erase pulse to the bit cell (20),
- determining a second value (Icell0) of the bit cell current (ICELL) flowing through the bit cell (20) and
- setting the bit cell (20) as a preselected bit cell, if a difference (ΔI) between the first value (Icell1) and the second value (Icell0) of the bit cell current (ICELL) is outside of a first predetermined current range.
12 more elements
A method for operating a memory arrangement, comprising
- storing information in a non-volatile memory plane in a write cycle, wherein the non-volatile memory plane comprises a second number M of preselected bit cells,
- counting the write cycle by one of a first number N of counters of a counter arrangement at a write cycle of a corresponding preselected bit cell of the second number M of preselected bit cells with the second number M equal or smaller than the first number N, and
- storing further information in a corresponding replacement bit cell of a replacement plane, if a counter value of said counter is higher than a predetermined limit corresponding to said preselected bit cell of the second number M of preselected bit cells, and in the non-volatile memory plane, if the counter value of said counter is equal or lower than the predetermined limit,
- wherein the memory arrangement comprises an address replacement plane that stores the addresses of the second number M of preselected bit cells,
- wherein the addresses of the second number M of preselected bit cells are determined in a test phase, the test phase is before an operation phase and the preselected bit cells are not changed in the operation phase,
- wherein an erase test of a bit cell is performed in the test phase by
- programming the bit cell,
- determining a first value of a bit cell current flowing through the bit cell,
- providing an erase pulse to the bit cell,
- determining a second value of the bit cell current flowing through the bit cell and
- setting the bit cell as a preselected bit cell, if a difference between the first value and the second value of the bit cell current is outside of a first predetermined current range.
8 more elements
Dependencies are inferred from the claim text.