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US 11,145,376 B1Granted
Memory system and method capable of performing wear leveling
AssigneeMacronix International Co., Ltd.
InventorChun-Lien Su
Life of this patent
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Abstract
A system includes a nonvolatile memory and a controller. The nonvolatile memory includes memory blocks. The controller is configured to perform at least one wear leveling operation, based on at least one degradation curve, to at least one of the plurality of memory blocks. Furthermore, a method associated with wear leveling is also disclosed herein.
Claims21
A system, comprising:
- a nonvolatile memory comprising a plurality of memory blocks;
- and
- a controller configured to perform at least one wear leveling operation, based on at least one degradation curve, to at least one of the plurality of memory blocks;
- wherein the at least one degradation curve indicates a degradation of a threshold voltage of the at least one of the plurality of memory blocks along with an increase of an erase count associated with the at least one of the plurality of memory blocks.
1 more element
A method, comprising:
- comparing a maximum erase count associated with a plurality of memory blocks in a nonvolatile memory with a first erase count threshold that is determined based on at least one degradation curve;
- and
- when the maximum erase count is greater than the first erase count threshold, performing at least one wear leveling operation to at least one of the plurality of memory blocks;
- wherein the at least one degradation curve indicates a degradation of a threshold voltage of the at least one of the plurality of memory blocks along with an increase of an erase count associated with the at least one of the plurality of memory blocks.
1 more element
A method, comprising:
- comparing erase counts associated with a plurality of memory blocks in a nonvolatile memory with an activation count threshold;
- when one of the erase counts is greater than the activation count threshold, determining a first erase count threshold according to at least one degradation curve associated with the plurality of memory blocks;
- comparing a maximum erase count associated with the plurality of memory blocks with the first erase count threshold;
- and
- when the maximum erase count is greater than the first erase count threshold, performing at least one wear leveling operation to at least one of the plurality of memory blocks;
- wherein the at least one degradation curve indicates a degradation of a threshold voltage of the at least one of the plurality of memory blocks along with an increase of an erase count associated with the at least one of the plurality of memory blocks.
3 more elements
Dependencies are inferred from the claim text.