Semiconductor memory device
AssigneeKioxia Corporation
InventorSanad Bushnaq
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device comprises a memory string that includes a plurality of memory cells electrically connected in series, the memory cells including first to fourth memory cells, first to fourth word lines that are electrically connected to gates of the first to fourth memory cells, respectively, a voltage generation circuit configured to generate a first voltage, a first circuit configured to output the first voltage to one of first and second wires, a second circuit configured to connect the first and second wires to the first and second word lines, respectively, and a third circuit configured to connect the first and second wires to the third and fourth word lines, respectively.
Claims16
A semiconductor memory device comprising:
- a bit line;
- a source line;
- a memory string that is provided between the bit line and the source line and includes a plurality of memory cells electrically connected in series, the memory cells including a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell;
- a plurality of word lines electrically connected to gates of the memory cells, respectively, the word lines including:
- a first word line connected to a gate of the first memory cell,
- a second word line connected to a gate of the second memory cell,
- a third word line connected to a gate of the third memory cell, and
- a fourth word line connected to a gate of the fourth memory cell;
- a voltage generation circuit configured to generate a plurality of first voltages;
- a first circuit configured to output the first voltages to one of a plurality of first wires;
- a second circuit configured to connect the first wires to one of a set of the first word line and the second word line, or a set of the third word line and the fourth word line, respectively;
- and
- a third circuit configured to connect a plurality of second wires to the other one of the set of the first word line and the second word line, or the set of the third word line and the fourth word line, respectively.
A method for controlling a semiconductor memory device including:
- a bit line;
- a source line;
- a memory string that is provided between the bit line and the source line and includes a plurality of memory cells electrically connected in series, the memory cells including a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell;
- and
- a plurality of word lines electrically connected to gates of the memory cells, respectively, the word lines including:
- a first word line connected to a gate of the first memory cell,
- a second word line connected to a gate of the second memory cell,
- a third word line connected to a gate of the third memory cell, and
- a fourth word line connected to a gate of the fourth memory cell,
- the method comprising:
- generating a plurality of first voltages;
- outputting the first voltages to one of a plurality of first wires;
- connecting the first wires to one of a set of the first word line and the second word line, or a set of the third word line and the fourth word line, respectively;
- and
- connecting a plurality of second wires to the other one of the set of the first word line and the second word line, or the set of the third word line and the fourth word line, respectively.
Dependencies are inferred from the claim text.