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US 11,145,369 B2Granted
Apparatuses and methods for adjusting write parameters based on a write count
AssigneeMicron Technology, Inc.
InventorsShekoufeh Qawami, Rajesh Sundaram
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Abstract
According to one embodiment of the present invention, an apparatus is disclosed. The apparatus includes a memory array having a plurality of memory cells. The apparatus further includes memory access circuits coupled to the memory array and configured to perform write operations responsive to control signals. The apparatus further includes control logic coupled to the memory access circuits and configured to apply a set of write parameters based, at least in part, on a number of write operations performed by the memory access circuits and further configured to provide control signals to the memory access circuits to perform write operations on the plurality of memory cells according to the set of write parameters.
Claims21
An apparatus comprising:
- a cross-point memory array having a plurality of memory cells;
- memory access circuits coupled to the memory array and configured to perform write operations responsive to control signals;
- control logic coupled to the memory access circuits and configured to provide control signals to the memory access circuits to perform write operations on the plurality of memory cells according to a respective set of write parameters;
- and
- a parameter table including a range of write operations for each of a plurality of write cycle bins, wherein the parameter table includes a minimum number of write operations and a maximum number of write operations for each of the plurality of write cycle bins, each write cycle bin of the plurality of write cycle bins based on a respective tolerance range of a plurality of tolerance ranges for a wear leveling scheme among the plurality of memory cells,
- wherein the control logic is configured to select the respective set of write parameters of a plurality of sets of write parameters based on an identified number of the write operations performed by the memory access circuits, and further based on the range of the write operations for each of the plurality of write cycle bins, wherein a first minimum number of the write operations and a first maximum number of the write operations of a first range define a first write cycle bin of the plurality of write cycle bins, wherein a second minimum number of the write operations and a second maximum number of the write operations of a second range define a second write cycle bin of the plurality of write cycle bins, and wherein the first maximum number of the write operations overlaps with the second minimum number of number of the write operations.
3 more elements
An apparatus comprising:
- a memory device including a plurality of memory cells and configured to store information on the plurality of memory cells based on a set of write parameters, and further including a parameter table, stored in a subset of the plurality of memory cells of the memory device, the parameter table configured to store a set of write cycle bins corresponding to the set of write parameters, each write cycle bin of the set of write cycle bins based on a respective tolerance range of a plurality of tolerance ranges for a wear leveling scheme among the plurality of memory cells,
- wherein a first minimum number of the write operations and a first maximum number of the write operations of a first range define a first write cycle bin of the set of write cycle bins, wherein a second minimum number of the write operations and second maximum number of the write operations of a second range define a second write cycle bin of the set of write cycle bins, and wherein the first maximum number of the write operations overlaps with the second minimum number of number of the write operations.
A method comprising:
- obtaining a number of write operations performed by a memory device;
- obtaining a parameter table defining a plurality of write cycle bins, each write cycle bin of the plurality of write cycle bins based on a respective tolerances range of a plurality of tolerance ranges for a wear leveling scheme among memory cells of the memory device;
- and
- selecting a write cycle bin of the plurality of write cycle bins based on the parameter table and the number of write operations,
- wherein a first minimum number of the write operations and a first maximum number of the write operations of a first range define a first write cycle bin of the plurality of write cycle bins, wherein a second minimum number of the write operations and a second maximum number of the write operations of a second range define a second write cycle bin of the plurality of write cycle bins, and wherein the first maximum number of the write operations overlaps with the second minimum number of number of the write operations.
2 more elements
Dependencies are inferred from the claim text.