Techniques for read operations

A method, comprising:

• outputting, by a first transistor coupled with a first node, a first voltage to the first node based at least in part on biasing a first gate of the first transistor to a second voltage;
• coupling a memory cell with the first node based at least in part on the first transistor outputting the first voltage to the first node;
• and
• outputting, by a second transistor, a third voltage to a second node coupled with the second transistor and a latch based at least in part on coupling the memory cell with the first node and biasing a second gate of the second transistor to a fourth voltage.

An apparatus, comprising:

• a memory cell;
• a controller coupled with the memory cell and configured to cause the apparatus to:
• output a first voltage to a first node based at least in part on biasing a first gate of a first transistor to a second voltage;
• couple the memory cell with the first node based at least in part on outputting the first voltage to the first node;
• and
• output a third voltage to a second node coupled with a second transistor and a latch based at least in part on coupling the memory cell with the first node and biasing a second gate of the second transistor to a fourth voltage.