Techniques to mitigate error during a read operation to a memory array
AssigneeIntel Corporation
InventorsDavide Mantegazza, Kiran Pangal
Life of this patent
Estimating the term…
Abstract
Examples may include techniques to mitigate errors during a read operation to a memory cell of a memory array. Examples include selecting the memory cell and applying one of multiple demarcation read voltages for respective multiple time intervals to sense a state of a resistive storage element of the memory cell. Examples also include applying a bias voltage to the memory cell following a sense interval to mitigate read disturb to the resistive storage element incurred while the one of the multiple demarcation read voltages was applied to the memory cell.
Claims23
An apparatus comprising:
- an interface to access memory cells of a memory array;
- and
- a controller, the controller to include logic, at least a portion of which is implemented as hardware, the logic to:
- select a memory cell from among the memory cells of the memory array to implement a read operation through the interface;
- apply, to the memory cell, one of a first demarcation read voltage (VDM), a second VDM or a third VDM for a respective first, second or third time interval to sense a state of a resistive storage element of the memory cell;
- and
- apply, to the memory cell, a bias voltage following the respective first, second or third time interval to mitigate read disturb to the resistive storage element incurred while the first, second or third VDM was applied to the memory cell.
A method comprising:
- selecting a memory cell included in a memory array;
- applying, to the memory cell, one of a first demarcation read voltage (VDM), a second VDM or a third VDM for a respective first, second or third time interval to sense a state of a resistive storage element of the memory cell;
- and
- applying, to the memory cell, a bias voltage following the respective first, second or third time interval to mitigate read disturb to the resistive storage element incurred while the first, second or third VDM was applied to the memory cell.
A system comprising:
- a memory array;
- an interface to access memory cells of the memory array;
- and
- a controller coupled with the interface, the controller to include logic, at least a portion of which is implemented as hardware, the logic to:
- select a memory cell from among the memory cells of the memory array;
- apply, to the memory cell, one of a first demarcation read voltage (VDM), a second VDM or a third VDM for a respective first, second or third time interval to sense a state of a resistive storage element of the memory cell;
- and
- apply, to the memory cell, a bias voltage following the respective first, second or third time interval to mitigate read disturb to the resistive storage element incurred while the first, second or third VDM was applied to the memory cell.
Dependencies are inferred from the claim text.