Nonvolatile memory apparatus for mitigating read disturbance and system using the same
AssigneeSK hynix Inc.
InventorsMoo Hui Park, Seok Joon Kang, Jun Ho Cheon
Life of this patent
Estimating the term…
Abstract
A nonvolatile memory apparatus may include a memory cell, a bit line control circuit, and a word line control circuit. The memory cell may be coupled between a global bit line and a global word line. During a read operation, the bit line control circuit may provide a first high voltage to the global bit line and provide a second high voltage to the global bit line when snapback of the memory cell occurs. During the read operation, the word line control circuit may provide a second read supply voltage to the global word line and provide an anneal supply voltage to the global word line when snapback of the memory cell occurs.
Claims19
A nonvolatile memory apparatus comprising:
- a memory cell coupled between a global bit line and a global word line;
- a bit line control circuit configured to provide a first high voltage to the global bit line based on a read signal and to provide a second high voltage to the global bit line based on a first control signal;
- a word line control circuit configured to provide a first low voltage to the global word line based on the read signal and to provide a second low voltage to the global word line based on a second control signal, and configured to control a first current to flow through the global word line based on the read signal and to control a second current to flow through the global word line based on the second control signal;
- and
- a sense amplifier configured to sense snapback of the memory cell and generate the first and second control signals,
- wherein the second current is larger than the first current, and the second current comprises an amount of current capable of setting the resistance state of the memory cell to a low resistance state.
An operation method of a nonvolatile memory apparatus, the method comprising:
- selecting a bit line to couple a memory cell to a global bit line, and selecting a word line to couple the memory cell to a global word line;
- applying a first high voltage to the global bit line and applying a first low voltage to the global word line, such that a first current flows through the memory cell, a voltage level difference between the first high voltage and the first low voltage corresponds to a voltage level of a read voltage;
- sensing whether snapback of the memory cell occurred;
- and
- applying a second high voltage to the global bit line and applying a second low voltage to the global word line, such that a second current flows through the memory cell, when the snapback of the memory cell occurred,
- wherein the second current is larger than the first current, and the second current comprises an amount of current capable of setting the resistance state of the memory cell to a low resistance state.
Dependencies are inferred from the claim text.