Memory device including discharge circuit
AssigneeSK hynix Inc.
InventorHyung Dong Lee
Life of this patent
Estimating the term…
Abstract
A memory device includes: first conductive lines extending in a first direction; second conductive lines extending in a second direction intersecting the first direction; a plurality of memory cells disposed at intersection portions of the first conductive lines and the second conductive lines; first selection transistors respectively connected to the first conductive lines, the first selection transistors constituting a plurality of groups; and first discharge circuits respectively connected to the plurality of groups of first selection transistors, each of the first discharge circuits discharging a group of first conductive lines corresponding thereto among the first conductive lines in response to a gate control signal.
Claims17
A memory device, comprising:
- a first deck including a first memory cell connected to a first deck-first conductive line;
- a second deck disposed over the first deck, the second deck including a second memory cell connected to a second deck-first conductive line;
- a third deck disposed over the second deck, the third deck including a third memory cell connected to a third deck-first conductive line;
- a fourth deck disposed over the third deck, the fourth deck including a fourth memory cell connected to a fourth deck-first conductive line;
- a first selection circuit including a first discharge circuit and first and second selection transistors respectively connected to the first deck-first conductive line and the third deck-first conductive line, the first discharge circuit commonly connected to the first and second selection transistors;
- and
- a second selection circuit including a second discharge circuit and third and fourth selection transistors respectively connected to the second deck-first conductive line and the fourth deck-first conductive line, the second discharge circuit commonly connected to the third and fourth selection transistors.
A memory device, comprising:
- a first deck including a first memory cell connected to a first deck-first conductive line extending in a first direction and a lower second conductive line extending in a second direction intersecting the first direction;
- a second deck disposed over the first deck, the second deck including a second memory cell connected to the lower second conductive line and a second deck-first conductive line extending in the first direction;
- a third deck disposed over the second deck, the third deck including a third memory cell connected to a third deck-first conductive line extending in the first direction and an upper second conductive line extending in the second direction;
- a fourth deck disposed over the third deck, the fourth deck including a fourth memory cell connected to the upper second conductive line and a fourth deck-first conductive line extending in the first direction;
- a first selection circuit configured to commonly control a discharge operation of the first deck-first conductive line and a discharge operation of the third deck-first conductive line, and individually control a selection operation of the first deck-first conductive line and a selection operation of the third deck-first conductive line;
- and
- a second selection circuit configured to commonly control a discharge operation of the second deck-first conductive line and a discharge operation of the fourth deck-first conductive line, and individually control a selection operation of the second deck-first conductive line and a selection operation of the fourth deck-first conductive line.
A memory device, comprising:
- first conductive lines extending in a first direction;
- second conductive lines extending in a second direction intersecting the first direction;
- a plurality of memory cells disposed at intersection portions of the first conductive lines and the second conductive lines;
- first selection transistors respectively connected to the first conductive lines, the first selection transistors constituting a plurality of groups;
- and
- first discharge circuits respectively connected to the plurality of groups of first selection transistors, each of the first discharge circuits discharging a group of first conductive lines corresponding thereto among the first conductive lines in response to a gate control signal,
- wherein each of the plurality of groups of first selection transistors includes two or more of the first selection transistors.
Dependencies are inferred from the claim text.