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US 11,145,358 B2Granted
Offsetting capacitance of a digit line coupled to storage memory cells coupled to a sense amplifier using offset memory cells
AssigneeMicron Technology, Inc.
InventorScott J. Derner
Life of this patent
Estimating the term…
Abstract
An apparatus includes a sense amplifier, a plurality of storage memory cells coupled to the sense amplifier via a first digit line, and a plurality of offset memory cells coupled to the sense amplifier via a second digit line. The plurality of storage memory cells and the plurality of offset memory cells can comprise an array of memory cells. Each of the storage memory cells and the offset memory cells can include a respective capacitor having a particular capacitance.
Claims12
An apparatus, comprising:
- a sense amplifier;
- a plurality of memory cells coupled to the sense amplifier via a first digit line and a second digit line,
- wherein the plurality of memory cells comprise:
- a plurality of storage memory cells coupled to the sense amplifier via the first digit line, wherein respective voltages held capacitively by the plurality of storage memory cells correspond to data values;
- and
- a plurality of offset memory cells coupled to the sense amplifier via the second digit line,
- wherein respective voltages held capacitively by the plurality of reference memory cells do not correspond to data values, and
- wherein a quantity of the plurality of offset memory cells is such that the plurality of offset memory cells provide a cumulative capacitance that is approximately equal to a capacitance of the first digit line;
- and
- a plurality of sense amplifiers at an edge of a memory array including the sense amplifier,
- wherein each sense amplifier of the plurality is coupled to a respective third digit line associated with a section of the memory array at the edge of the memory array and a respective fourth digit line associated with the section of the memory array at the edge of the memory array,
- wherein the respective third digit line is coupled to at least one storage memory cell, and
- wherein the respective fourth digit line is coupled to at least one offset memory cell.
10 more elements
A method, comprising:
- selectively coupling a particular quantity of memory cells of an array of memory cells to a first conductive line coupled to a sense amplifier,
- wherein the particular quantity of memory cells is such that the selectively coupled memory cells provide a cumulative capacitance that is approximately equal to a capacitance of a second conductive line coupled to the sense amplifier, and
- wherein respective voltages held capacitively by the selectively coupled memory cells do not correspond to data values;
- and
- offsetting a voltage differential of the sense amplifier with a cumulative voltage held capacitively by the selectively coupled memory cells, wherein offsetting the voltage differential of the sense amplifier includes:
- enabling a pair of transistors, at a first time, to place a voltage across the selectively coupled memory cells;
- disabling the pair of transistors, at a second time subsequent to the first time, to maintain the voltage across the selectively coupled memory cells;
- and
- enabling the pair of transistors at a third time subsequent to the second time and concurrent with sensing a data value stored by storage memory cells of the array of memory cells coupled to the sense amplifier.
6 more elements
An apparatus, comprising:
- an array of memory cells formed on a CMOS layer,
- wherein the array includes:
- a plurality of storage memory cells coupled to a first conductive line via a first plurality of vertical pillar access devices,
- wherein respective voltages held capacitively by the plurality of storage memory cells correspond to data values;
- and
- a plurality of offset memory cells coupled to a second conductive line via a second plurality of vertical pillar access devices,
- wherein respective voltages held capacitively by the plurality of reference memory cells do not correspond to data values, and
- wherein a quantity of the plurality of offset memory cells is such that the plurality of offset memory cells provide a cumulative capacitance approximately equal to at least a capacitance of the first conductive line;
- and
- wherein the CMOS layer includes a sense amplifier coupled to the first and second conductive lines;
- and
- a controller coupled to the array of memory cells and configured to:
- selectively couple at least one of the offset memory cells to the second conductive line;
- and
- apply a signal to a word line of the array of memory cells to which the at least one of the offset memory cells are coupled to selectively couple the at least one of the offset memory cells to the second conductive line.
12 more elements
Dependencies are inferred from the claim text.