Centralized DFE reset generator for a memory device
AssigneeMicron Technology, Inc.
InventorsWilliam Chad Waldrop, Daniel B. Penney
Life of this patent
Estimating the term…
Abstract
Systems and methods are provided that include an interamble data strobe (DQS) counter configured to count cycles between write operations. The interamble DQS counter includes a decision feedback equalizer (DFE) reset mask circuit configured to generate a DFE reset enable signal and a DFE reset timing generator configured to generate timing signals for the DFE reset. The systems and methods also include a DFE reset generator configured to receive the DFE reset enable signal and the timing signals from the interamble DQS counter, to use the DFE reset enable signal and the timing signals to generate DFE reset signals for a plurality of DQS phases; and to transmit the DFE reset signals to the plurality of DQS phases.
Claims19
A memory device, comprising:
- an interamble data strobe (DQS) counter configured to count cycles between write operations, wherein the interamble DQS counter comprises:
- a decision feedback equalizer (DFE) reset mask circuit configured to generate a DFE reset enable signal;
- and
- a DFE reset timing generator configured to generate timing signals for the DFE reset;
- a DFE reset generator configured to:
- receive the DFE reset enable signal and the timing signals from the interamble DQS counter;
- use the DFE reset enable signal and the timing signals to generate DFE reset signals for a plurality of DQS phases;
- and
- transmit the DFE reset signals to the plurality of DQS phases, wherein the DFE reset signals are configured to drive the DFE resetting for a first half of a prefetch for the memory device.
A semiconductor device, comprising:
- a centralized decision feedback equalizer (DFE) reset generator configured to:
- generate a plurality of DFE reset signals;
- and
- transmit the plurality of DFE reset signals to a plurality of data strobe (DQS) phases to control whether to reset respective DFEs of the plurality of DQS phases;
- and
- a plurality of buffer and chop circuits located in the plurality of DQS phases, wherein each buffer and chop circuit of the plurality of buffer and chop circuits is configured to receive:
- a data input buffer signal to selectively cause persistent enablement of a DFE reset of a respective DFE;
- and
- a respective DFE reset signal of the plurality of DFE reset signals to selectively reset the respective DFE based at least in part on the respective DFE reset signal.
A method, comprising:
- generating a decision feedback equalizer (DFE) reset enable signal and timing signals at an interamble DQS counter;
- transmitting the DFE reset enable signal and the timing signals to a DFE reset generator;
- using the DFE reset generator, generating a DFE reset signal for a plurality of data strobe (DQS) phases of a memory device, wherein a first copy of the DFE reset signal is transmitted to a first DQS phase of the plurality of DQS phases on a first side of the DFE reset generator, and a second copy of the DFE reset signal is transmitted to a second DQS phase of the plurality of DQS phases on a second side of the DFE reset generator, wherein the first DQS phase and the second DQS phase correspond to similar phases on opposite sides of the DFE reset generator;
- and
- selectively resetting DFEs of the plurality of DQS phases using the DFE reset signal.
Dependencies are inferred from the claim text.