Physically unclonable function architecture including memory cells with parallel-connected access transistors and common write wordlines

A circuit comprising:

• an array of memory cells arranged in columns and rows, wherein each memory cell comprises:
• multiple variable resistors comprising:
• a first variable resistor;
• and a second variable resistor;
• and
• multiple transistors comprising:
• two parallel-connected first transistors;
• and two parallel-connected second transistors, wherein the first transistors and the first variable resistor are connected in series between a bitline and a source line and the first transistors have gates connected to a common write wordline and to a first read wordline, respectively, and wherein the second transistors and the second variable resistor are connected in series between the bitline and the source line and the second transistors have gates connected to the common write wordline and to a second read wordline, respectively.

A method comprising:

• providing an array of memory cells arranged in columns and rows, wherein each memory cell comprises:
• multiple variable resistors comprising:
• a first variable resistor;
• and a second variable resistor;
• and
• multiple transistors comprising:
• two parallel-connected first transistors;
• and two parallel-connected second transistors, wherein the first transistors and the first variable resistor are connected in series between a bitline and a source line and the first transistors have gates connected to a common write wordline and to a first read wordline, respectively, and wherein the second transistors and the second variable resistor are connected in series between the bitline and the source line and the second transistors have gates connected to the common write wordline and to a second read wordline, respectively;
• and
• operating each memory cell in an initialization mode, wherein the operating of the memory cell in the initialization mode comprises:
• causing a write process to be performed to achieve one-time programming of the memory cell from an unprogrammed state to a random programmed state by applying write bias conditions on the bitline and the source line connected the memory cell and activating the common write wordline connected to the memory cell such that, in response to the write bias conditions and activation of the common write wordline and further given existence of random process variations in the memory cell, the memory cell switches from the unprogrammed state to the random programmed state.