Circuit structure and method for memory storage with memory cell and MRAM stack

A circuit structure comprising:

• a static random access memory (SRAM) cell having a first inverter configured to store a first logic voltage and a second inverter configured to store a second logic voltage;
• a first magnetic random access memory (MRAM) stack coupled to the first inverter of the SRAM cell through a first access transistor;
• a second MRAM stack coupled to the second inverter of the SRAM cell through a second access transistor, wherein each of the first MRAM stack and the second MRAM stack include:
• a first layer and a second layer each having a respective magnetic moment, wherein the magnetic moment of the second layer is adjustable between a parallel orientation and an antiparallel orientation with respect to the magnetic moment of the first layer, in response to an applied voltage;
• and
• a spin Hall electrode coupled to the first MRAM stack and the second MRAM stack, and between a pair of switches for selectively applying a write current through the spin Hall electrode, wherein a magnitude of the write current induces a spin Hall transfer to the second layer of each MRAM stack to store the first logic voltage in the first MRAM stack, and the second logic voltage in the second MRAM stack.

A method for recording data within an integrated circuit (IC) structure, the method comprising:

• providing a circuit structure including:
• a plurality of latches electrically coupled to another component of the IC structure, and configured to store a plurality of digital bits,
• a first plurality of magnetic random access memory (MRAM) stacks coupled to one of the plurality of latches, each MRAM stack of the first plurality of MRAM stacks including:
• a first layer having a first magnetic moment in a first orientation, and
• a second layer on the first layer, and having a second magnetic moment adjustable between the first orientation and a second orientation opposite the first orientation, in response to an applied voltage, and
• a spin Hall electrode directly coupled to each MRAM stack of the first plurality of MRAM stacks, wherein each of the first plurality of MRAM stacks is coupled between the spin Hall electrode and one of the plurality of latches;
• transmitting a read current from the memory cell to a selected one of the first plurality of MRAM stacks;
• and
• transmitting a write current across the spin Hall electrode, wherein transmitting the write current records the plurality of digital bits from the plurality of latches within the first plurality of MRAM stacks.