Memory device
AssigneeKioxia Corporation
InventorYorinobu Fujino
Life of this patent
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Abstract
According to one embodiment, a device includes a first cell between first and second interconnects; a second cell between second and third interconnects; a third cell between fourth and fifth interconnects; a fourth cell between fifth and sixth interconnects; a equalization circuit connected to the first to sixth interconnects; and a control circuit controlling operation on the first to fourth cells. During the operation, the control circuit applies a first voltage to the first interconnect, applies a second voltage higher than the first voltage to the second interconnect, applies a third voltage to the fifth interconnect, and applies a fourth voltage higher than the third voltage to the sixth interconnect. After the operation, the equalization circuit connects the first interconnect to the sixth interconnect.
Claims20
A memory device comprising:
- a first memory cell provided between a first interconnect and a second interconnect;
- a second memory cell provided between the second interconnect and a third interconnect;
- a third memory cell provided between a fourth interconnect and a fifth interconnect;
- a fourth memory cell provided between the fifth interconnect and a sixth interconnect;
- a first equalization circuit connected to the first, third, fourth, and sixth interconnects;
- and
- a control circuit configured to perform a control operation on the first to fourth memory cells,
- wherein:
- during execution of the control operation, the control circuit:
- selects the first and fourth memory cells,
- applies a first voltage to the first interconnect,
- applies a second voltage higher than the first voltage to the second interconnect,
- applies a third voltage lower than the second voltage to the fifth interconnect, and
- applies a fourth voltage higher than the third voltage to the sixth interconnect, and
- after execution of the control operation, the first equalization circuit electrically connects the first interconnect to the sixth interconnect.
A memory device comprising:
- a first memory cell provided between a first interconnect and a second interconnect;
- a second memory cell provided between the second interconnect and a third interconnect;
- a third memory cell provided between a fourth interconnect and a fifth interconnect;
- a fourth memory cell provided between the fifth interconnect and a sixth interconnect;
- a first equalization circuit connected to the first, third, fourth, and sixth interconnects;
- and
- a control circuit configured to perform a control operation on the first to fourth memory cells,
- wherein:
- during execution of the control operation, the control circuit:
- selects the first and fourth memory cells,
- applies a first voltage to the first interconnect,
- applies a second voltage higher than the first voltage to the second interconnect,
- applies a third voltage lower than the second voltage to the fifth interconnect, and
- applies a fourth voltage higher than the third voltage to the sixth interconnect, and
- after execution of the control operation, the first equalization circuit electrically connects the second interconnect to the fifth interconnect.
Dependencies are inferred from the claim text.