Method for controlling multi-cycle write leveling process in memory system
AssigneeFaraday Technology Corp.
InventorsSivaramakrishnan Subramanian, Hong-Yi Wu, Sridhar Cheruku, Ko-Ching Chao
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Abstract
A method for controlling a multi-cycle write leveling process in a memory system is provided. After a write leveling process is completed and before a write training process is performed, the multi-cycle write leveling process is performed. Consequently, when a DDR memory of the memory system receives a clock signal and a first data strobe signal, the DDR memory can confirm that the signal edges of the clock signal and the first data strobe signal are aligned with each other and the signal edges are accurate.
Claims9
A method for controlling a multi-cycle write leveling process in a memory system, the memory system comprising a DDR memory, the method comprising steps of:
- (a) storing a write data into the DDR memory, and reading the write data from the DDR memory;
- (b) judging whether the write data stored in the DDR memory and the write data read from the DDR memory match each other to generate a data match event, wherein if the data match event is not generated, judging whether a first delaying time of a data signal has been adjusted to a first upper limit;
- (c) if the first delaying time of the data signal has not been adjusted to the first upper limit, increasing the first delaying time of the data signal and then going back to the step (a);
- (d) if the first delaying time of the data signal has been adjusted to the first upper limit, judging whether a second delaying time of a first data strobe signal has been adjusted to a second upper limit;
- (e) if the second delaying time of the first data strobe signal has not been adjusted to the second upper limit, increasing the second delaying time of the first data strobe signal and then going back to the step (a);
- (f) if the second delaying time of the first data strobe signal has been adjusted to the second upper limit, judging whether a third delaying time of an address/command signal has been adjusted to a third upper limit;
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- (g) if the third delaying time of the address/command signal has not been adjusted to the third upper limit, increasing the third delaying time of the address/command signal and then going back to the step (a).
Dependencies are inferred from the claim text.