Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle

An apparatus, comprising:

• a memory;
• a command/address bus;
• a data bus;
• clock bus;
• and
• a memory controller coupled to the memory through the command/address bus, the data bus, and the clock bus, the memory controller configured to;
• issue a first plurality of commands to a memory to perform a first plurality of duty cycle monitor sequences to identify a first duty cycle adjuster code having first duty cycle results that are determinate and that border a first indeterminate duty cycle adjuster code having first indeterminate duty cycle results;
• issue a second plurality of commands to the memory to perform a second plurality of duty cycle monitor sequences to identify a second duty cycle adjuster code having second duty cycle results that are determinate and that border a second indeterminate duty cycle adjuster code having second indeterminate duty cycle results;
• and
• set the duty cycle adjuster code to an intermediate step between the first duty cycle adjuster code and the second duty cycle adjuster code.

A method, comprising:

• receiving a first plurality of commands from a memory controller at a memory;
• responsive to the first plurality of commands:
• setting a duty cycle adjuster code of a duty cycle adjuster circuit to a first plurality of values;
• performing a first plurality of duty cycle monitor sequences with a duty cycle monitor circuit and provide a first plurality of duty cycle results corresponding to the first plurality of values of the duty cycle adjuster code;
• receiving a second plurality of commands at the memory;
• responsive to the second plurality of commands:
• setting the duty cycle adjuster code to a second plurality of values;
• performing a second plurality of duty cycle monitor sequences with the duty cycle monitor circuit to provide a second plurality of duty cycle results corresponding to the second plurality of values of the duty cycle adjuster code;
• receiving a third command at the memory;
• and
• responsive to the third command, setting the duty cycle adjuster code to an intermediate step between a first duty cycle adjuster code and a second duty cycle adjuster code,
• wherein the first duty cycle adjuster code is one of the first plurality of duty cycle adjuster codes having a result of the first plurality of duty cycle monitor results that is determinate and borders a first indeterminate duty cycle adjuster code having first indeterminate duty cycle results, and
• wherein the second duty cycle adjuster code is one of the second plurality of duty cycle adjuster codes having a result of the second plurality of duty cycle monitor results that is determinate and that borders a second indeterminate duty cycle adjuster code having second indeterminate duty cycle results.