Data transmission code and interface

A data receiving interface for use in a second integrated circuit, IC, configured to receive and decode a data packet sent from a first IC to the second IC via a data bus having three data wires, the data receiving interface arranged to receive three time-dependent binary signals which jointly encode the data packet, each of the signals being associated with a unique wire of the data bus and spanning a temporal cycle T within which are defined six consecutive time stamps T1 . . . T6 at which the signals are allowed to change logical state, the data receiving interface further arranged to decode the data packet from the three signals, wherein, irrespective of the data packet content:

• at each time stamp T1 . . . T6 exactly one of the signals changes logical state;
• each signal changes logical state twice during the cycle T;
• and
• in the first half of the cycle T, all signals change from a logical low state to a logical high state or all signals change from a logical high state to a logical low state.

A system comprising a first device, a second device and a data bus comprising three data wires, the first device and the second device being connected to the data bus,

• the first device comprising a data transmission interface operable to generate three time-dependent binary signals which jointly encode a data packet, each of the signals spanning a temporal cycle T within which are defined six consecutive time stamps T1 . . . T6 at which the signals are allowed to change logical state, the data transmission interface being operable to transmit the three signals to the second device substantially in parallel on respective data wires of the data bus,
• the second device comprising a data receiving interface operable to receive the three signals on the data bus and to decode the data packet from the three signals, wherein, irrespective of the data packet content:
• at each time stamp T1 . . . T6 exactly one of the signals changes logical state;
• each signal changes logical state twice during the cycle T;
• and
• in the first half of the cycle T, all signals change from a logical low state to a logical high state or all signals change from a logical high state to a logical low state.